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From YouTube: CHIPS Alliance - Analog Working Group - 2021-05-10
Description
Learn more at https://chipsalliance.org
A
A
A
B
My
powerpoint
here
all
right,
so
I
pulled
together
a
few
slides.
These
are
taken
from
various
you
know,
prior
presentations
on
on
cell-based,
analog
circuit
design
that
my
group
has
been
working
on
at
michigan
for
a
while,
as
well
as
more
recently
on
the
fa.
Sac
program,
which
I
think
is
is
probably
what
most
of
you
are
are
at
least
more
familiar
with.
If
you've
heard
of
that,
maybe
for
betty
last
time.
B
So
so
I'll
walk
you
through,
you
know
kind
of
a
bit
of
a
little
bit
of
the
history,
but
then
focus
more
on
just
what
fa
sock
is
and
what
we're
doing
with
it
today
and
feel
free
to
stop.
If
you
have
any
questions
so
high
level
high
level
overview,
fa
stock
is
short
for
fully
autonomous
soc
synthesis
and
what
it
is
is
a
set
of
tools
really
scripts,
that
ride
on
top
of
digital
synthesis
and
apr
tools.
B
But
it's
a
set
of
tools
that
allow
you
to
synthesize,
complete
soc
designs
by
using
correct
by
construction,
soc
design,
meaning
by
putting
the
blocks
together.
You
know
ensuring
that
you
have
interoperability
between
the
blocks
and
we
leverage
ipxact
for
specification
of
the
blocks
and
arm
socrates
for
doing
the
floor
planning
and
the
stitching
socrates
has
been
modified
to
include
floor
planning
for
this
program.
B
Otherwise,
in
the
beginning,
just
using
that
for
stitching
and
then
we
have
a
whole
suite
of
analog
generators,
and
this
this
is,
the
suite-
has
been
growing
over
time.
So
we've
added
just
since
fa
socket
started.
We've
added
a
couple
to
this
list,
but
really
these
are
the
the
red
blocks
down
at
the
bottom,
and
this
is
the
focus
of
the
talk
today.
Is
I
want
to
get
into
what
what
is
cell
based
analog
design
or
what
are
these
cell-based
analog
generators?
What
do
they
do?
How
do
they
work?
B
Since
I
think
this
this
group
is
much
more
focused
on
on
that
or
much
more
interested
in
that
right
now,
so
so
that's
fba
stock
at
a
high
level,
so
we'll
dig
into
we'll
dig
into
the
analog
generators,
and
just
I
this
audience.
I
think
all
knows
this,
but
I
just
want
to
make
this
point,
because
this
is
really
where
this
was
born.
From
was
when
you
look
at
analog
and
digital
design
flows
today.
Most
of
analog
design
is,
is
custom,
media
or
done
by
hand,
meaning
the
white
blocks.
B
The
green
blocks
here
are
automated
and
most
of
the
digital
design
flow
is
automated
and
that's
been
true
for
a
long
time.
So
we
looked
at
that
many
years
ago
and
said
well.
If
we
could
just
leverage
the
digital
flow
and
the
existing
digital
tools,
then
perhaps
we
have
a
shot
at
automating,
the
physical
design
or
automating
the
layout
of
an
analog
circuit.
B
So
so
really
the
whole
goal
here
is
to
try
and
take
what
would
otherwise
be
a
full
custom,
analog,
design
and
shoehorn
it
in
to
the
cell-based
digital,
automated
design
flow
methodology.
And
if
we
can
do
that,
then
we
can
leverage
today's
tools
or
future
tools
that
are
geared
towards
digital
design.
B
So
luckily,
for
us
there
are
digital
tools
that
can
do
all
of
that
for
us,
so
all
right,
so
I'll
start
with
just
an
intro
of
what
is
cell-based,
synthesizable
analog
design.
So
we
I
I'll,
also
sometimes
call
this
vlsa
vlsa
stands
for
very
large
scale.
Analog
it's
a
play
on
vlsi,
but
vlsa
is
what
we're
calling
this
before
fa
sac.
B
But
what
is
vlsa
so
our
goal
for
vlsa
is
to
describe
an
analog
block
in
verilog.
It
could
be
a
combination
of
structural
verilog
or
behavioral
verilog,
where,
with
structural
varilog,
we
might
pluck
specific
cells
out
of
a
standard
cell
library
or
a
library.
That's
been
augmented
with
a
couple
couple:
additional
cells,
auxiliary
cells,
I'll
call
them,
but
pluck
these
cells
out
and
wire
them
up,
you
know
how
you
would
like
in
order
to
implement
an
analog
circuit,
but
to
do
that
using
verilog,
a
verilog
hardware
description
language.
B
So
that's
our
goal
is:
if
we
can
describe
an
analog
circuit
with
verilog,
then
we
have
a
shot
of
running
that
through
the
digital
tool
flow.
So
I
mentioned
auxiliary
cells.
So
really
this
is
optional.
Some
sometimes
you
can
complete
this
design
with
just
what's
in
a
standard
cell
library
other
times
it's
not
enough.
You
want
to
add
a
couple
cells
to
it.
A
A
Quick
question
so
the
I'm
just
curious
about
the
usage
of
behavioral
verilog.
So
I
know
that
you
know.
Verification
of
analog
designs
is
always
a
challenge
and
I
know
there's
been
work
done
to
come
up
with
behavioral
descriptions
of
analog
design.
My
former
group
that
I
had
at
oracle.
We
were
doing
that
using
matlab
and
then
coupling
that
with
vcs.
So
is
that
kind
of
a
similar
thought
process
relative
to
a
behavioral
description
or.
B
B
So,
okay,
you
can
you
can
use
your
your
standard
more,
you
know
higher
level
or
abstracted
verilog
to
code
up,
let's
say
calibration
circuits,
or
you
know
built-in
tests,
for
example,
or
design
for
test
circuits
other
circuits
that
might
augment
the
the
the
core
analog
block.
So
you
we
combine
these
things
together
and
we
run
them
through
the
tool
flow.
So
not
so
not
modeling
or
high
level
user
spec
description,
but
just
low-level
verilog
coding
is
what
I'm
referring
to
there.
Okay,
thank
you.
B
C
B
Flop
here
or
put
a
tri-state
buffer
here
that
structural
verilog,
it's
really
annoying,
but
it
lets
you
pick
specific
cells
and
wire
them
up
exactly
how
you
want,
and
then
you
can
tell
the
tool
to
not
touch
it.
Don't
optimize,
don't
treat
that,
like
logic,
don't
optimize
any
of
the
anything
I
just
did
just
leave
it,
but
then
I'm
going
to
combine
that
with
a
bunch
of
other.
Let's
say,
digital
functions,
adders
multipliers,
whatever
you
know
when
behavioral
verilog
around
that
to
complete
the
whole
design.
B
Yes,
thank
you.
So
here's
an
example
just
getting
to
that.
So,
for
example,
I
could
take
n
tri-state
buffers
and
I
could
hook
them
all
up
in
parallel.
Like
this,
all
the
inputs
connected
together,
all
the
outputs
connected
together
and
then
I
individually
drive
the
enables
of
those
and
gates.
I'm
sorry,
those
tri-state
buffers,
and
that
gives
me
a
a
digital
control
over
the
delay
across
this
block,
and
I
can
do
that
by
just
taking
structural
verilog
and
wiring
up
tri-state
buffers
from
a
standard.
Most
standard
cell
libraries
have
them,
then
I
can
take.
B
So
now
I
have
structural
verilog
that
is
parameterized
and
buffers
per
stage
and
s
stages,
where
I
can
now.
I
can
fill
in
the
blanks
for
n
and
s
and
produce
an
arbitrary
number
of
stages,
with
an
arbitrary
number
of
buffers
per
stage
produce
the
structural
varilog
to
describe
that
dco.
I
can
then
run
that
through
an
apr
flow
and
it'll
drop
down
the
tri-state
buffers
and
wire
them
up.
Just
like
I,
I
coded
you
produce
gds
and
it
looks
a
lot
like
digital
gds.
B
B
B
All
right,
okay,
so
I
mentioned
that's
where
we
started
so
here's
kind
of
the
evolution
of
this.
So
we
started
literally
with
tristate
buffers
pulled
from
a
tsmc
standard
cell
library
and
we
built
plls
with
that.
We
built
an
ultra
wide
band
transmitter
with
that.
We
built
an
fm
radio
receiver
with
that.
B
So
we
we
built
differential,
tristate
buffers
where
now,
instead
of
a
single-ended
tri-state,
it's
a
it's
a
differential
circuit,
but
it's
tri-stateable,
and
that
gives
you
some
power
supply
rejection,
for
example,
and
then
we
we
implemented
a
simple
switch
and
capacitor
a
mos
capacitor
and
a
pass
gate
switch
three
transistors,
for
example,
and
that
gives
you
finer
resolution
of
the
delay
per
stage.
So
now
with
differential,
tri-state
buffers
and
switch
caps,
you
can
now
have
a
differential
oscillator
with
finer
resolution
finer
control
over
the
over
the
frequency
or
delay
per
stage.
B
All
right,
then,
then
we
started
looking
at
modeling
because
now
getting
back
to
the
earlier
question
about
behavioral
modeling,
we
started
looking
at
modeling
because
you
know
these
circuits
were
getting
more
and
more
complex,
bigger
and
bigger.
We
wanted
to
synthesize
the
analog
circuit
with
the
digital
stuff
around
it,
and
then
we
wanted
to
know
the
performance
post
pex
after
layout.
We
wanted
to
extract
all
rcs
and
then
re-simulate,
and
that
was
getting
a
bit
cumbersome.
So
we
started
looking
at
modeling
and
ways
to
improve
that
design
flow.
B
That's
that's
moved
into
fa
sock
now
and
and
then
now,
with
fa
sock.
We're
also
looking
at
things
like
scripted
cell
placement,
so
using
python,
for
example,
to
put
more
regular
cell
placement
again
they
are,
their
cells,
are
standard
cells
or
they're
on
the
standard
cell
grid.
They
follow
the
center
cell
rule,
so
you
can
abut
them.
You
know
you
can
array
them
and
they
will
pass
drc
and
that
they
can
sit
along
with
other
digital
or
other
standard
cells.
Just
fine.
B
So
we
started
looking
at
things
like
custom
cell
placement
with
scripts,
where
you
can
again
parameterize
your
scripts
but
then
lay
out
a
more
regular
grid
of
the
most
critical
cells
and
that's
how
we
continue
to
improve
the
performance
of
these
analog
blocks.
I'll
show
you
some
examples
of
that
later,
all
right,
so
I
kind
of
think
of
this
as
a
pendulum
swinging.
So
we
started
on
the
left.
B
B
You're,
just
writing
verilog
at
this
point,
but
the
performance
took
a
hit,
and
so
now
we've
swung
that
pendulum
back
to
somewhere
in
the
middle,
where
we're
using
auxiliary
cells
and
partial
placement
of
those
cells
with
scripting
to
kind
of
get
the
best
of
both
worlds.
You
you
it's
significantly
lower
complexity
than
trying
to
use
an
analog
layout
tool
to
do.
You
know
analog
design,
more
traditional
analog
design,
but
it's
it's.
It's
not.
C
The
middle:
do
you
in
the
scripts
part
of
this?
This
are
they
scripts
that
are
like
custom
or
just
around
configurations
and
constraints
and
set
up
around
an
existing
digital
flow
yeah
like
the
placement
part,
they
actually
have
a
placement
placer,
or
is
it
just
again
using
the
engines
of
the
digital,
with
different
constraints
or
different
maddie?
You
want
to
answer
that
question.
C
C
B
Two
yeah
I'd
say:
that's
similar,
actually
I'll
show
you
an
example
later
of
what
those
look
like,
but
yeah
similar
you
know
to
like
to
what
maddie
was
saying.
You
know
we
would
use
python
for
placing
most
critical
cells
like,
for
example,
the
the
delay
cells,
the
the
tristate
dip,
the
tristate
buffers
and
the
switch
caps
in
a
digitally
controlled.
Oscillator
we'd
place
those
with
python
in
an
array
where
they
abut
next
to
one
another
right,
but
then
we
would.
B
You
know
we
can
use
things
like
attractors
to
pull
those
together
like
you
can
tell.
You
can
usually
tell
these
apr
tools
to
like
pull
all
the
pull
all
the
cells
put
all
cells.
Next
to
a
pin.
You
know
it's
like
these
cells
are
critical,
or
this
net
is
critical
for
anything
touching.
This
net
put
them
as
close
as
you
can,
and
at
least
we've
been
able
to
do
that
with
pins.
B
So
that's
modifying
existing
tools
and
today
we're
using
commercial
tools
at
michigan.
Well,
I'd
say:
the
cadre
flow
was
developed
in
rhonda
drezelinski's
group
and
that
uses
commercial
tools,
and
we
are
we've
already
demonstrated
this
with
open
source.
Medi
has
been
doing
that.
I'm
sorry
with
open
road.
Many
has
been
doing
that
he's
been
spearheading
that
and
there
so
there's.
B
C
All
right
by
the
way,
just
michael
mentioned
something,
and
I
I
fall
into
the
trap,
all
the
time:
commercial,
there's,
proprietary
and
open
source
both
can
be
commercial,
so
so
we're
trying
to
set
that
tone
like,
especially
for
a
company
like
ours
e-fabulous.
We
use
all
the
open
source
tools
to
provide
commercial.
You
know
tips.
F
C
C
B
Yeah,
we
absolutely
appreciate
you
know
everything
you're
doing
to
pull
fast
in
and
and
the
feedback
is
very
valuable
too,
and
let
me
let
me
let
me
be
more
specific,
like,
for
example,
innovus.
We
use
innovis
a
cadence
tool,
so
so
we
pay
for
those
tools
so
they're
paid.
You
know
commercial
tools,
proprietary
tools
and
the
scripts
or,
I
should
say
the
commands
that
are
that
are
used
in
scripts
to
drive.
B
C
Okay,
well
and
thank
you
and
I
didn't
mean
to
derail
the
conversation
yeah,
it's
where
I'm
watching
the
progress
and
I'm
just
letting
you
know
that
you
know
it's
it's
a
I'm.
I
come
from
a
hardcore
animal
background.
Yeah,
I'm
also
a
believer
in
so
because
I
I
know
you
know
what
they're
doing
you
will
produce
things
that
work
and
reliably
and
consistently.
Yes,.
B
Yeah
me
too,
I
came,
I'm
a
hardcore
analog
background
so
and
so,
and
I've
gone
through
the
pain
of
design
and
layout
of
analog
circuits,
which
is
why
you
know
this
is
so
attractive
to
me.
It's
why
we're
working
on
this,
so
all
right
so
pulling
us
back.
So
here's
our
our
analog
design
flow
kind
of
from
left
to
right
the
the
entire
design
flow
for
any
of
our
analog
blocks.
We
adopt
the
same
thing
for
all
the
blocks
you
can
see
down
here
on
this
first
bullet,
the
pll
adc
cdc.
B
All
these
blocks
use
the
same
flow
where
there's
some
there's
some
one-time
setup
that
we
do
in
order
to
port
to
a
new
process
and
then
there's
the
every
time
you
want
to
generate
a
circuit.
You
would
run
this
part
on
the
right,
so
the
one
time
setup
is
our
aux
cell
generation.
So,
for
example,
the
layout
of
an
auxiliary
cell
would
be
done
once
when
you
port
to
the
process.
We
also
do
some
modeling
and
this
varies
by
block,
but
but
sometimes
this
is
ml
based
modeling.
B
Sometimes
it's
more
like
a
physics
based
modeling,
but
we
generate.
We
generate
multiple
designs
using
our
scripts.
We
simulate
those
designs
post
pex,
we
take
those
simulation
results
and
we
use
them
to
somehow
create
a
model
for
each
generator
again
done
once
when
you
port
and
then
once
you
have
the
model
and
the
aux
cell
library
you
can
go
generate.
You
know
you
can
put
in
your
user
specs
and
you
can
generate
whatever
block
you
want
with
whatever
specs
you
want.
B
As
long
as
they're
achievable
with
that
design,
you
run
that
through
digital
synth
and
apr
you
get
gds,
you
do
post
pex
extraction,
you
simulate
post
packs.
You
can
do
whatever
verification
you
want.
Any
verification,
you'd
normally
do
on
an
analog
block.
You
can
do
it
on
this
postpecs
design,
that's
what
we
do
and
then,
if
once
it
meets
your
specs,
then
we
add
it
to
this
library.
B
We
call
it
our
cots
library,
commercial
off
the
shelf
library,
but
we
add
it
to
a
library
of
blocks
that
we've
now
designed
and
verified
and
now
fa
stock.
The
high
level,
the
soc
generator
can
pull
from
that
pull
from
that
library.
If
it
exists
already
or
if
it
doesn't,
it
can
go,
call
an
analog
generator
to
create
the
block
and
then
pull
it
in
after
it's
been
created.
That's
that's.
Basically,
our
flow.
A
B
Spice
simulation,
although
we
are
looking
at
to
to
speed
up
the
modeling
of
our
timing
circuits,
specifically
like
dlls
plls
things
like
that,
we
are
looking
at
the
the
mod
the
timing.
Information
generated
by
a
tool
like
liberate
went
in
yeah.
So
we
are
we're
looking
at
that,
because
it
because
there
are,
you
know
when
you
lay
these
out
like
the
the
timing.
B
Information
that
gets
generated
is
pulled
from
all
this
data
that
comes
out
of
these
cells,
and
we've
been
comparing
that,
with
some
of
the
spice
level
sims
of
some
again
timing
based
circuits
like
oscillators
or
delay,
lines,
long
delay,
lines
and
they're
pretty
good
at
predicting
what
the
performance
will
be
so
we're
looking
at.
You
know
how
accurate
that
would
be
if
we
just
skip
the
whole
spice
sim
part
and
just
use
the
characterization.
B
A
A
Another
approach
that
another
approach
that
we
had
looked
at
in
back
in
my
industrial
days
was
we
had
a
mixed.
We
had
a
mixed
mode
capability
for
our
gate
analysis
tool
so
that,
depending
upon
what
the
design
was
in
particular
such
as
the
clock
grid,
we
actually
were
able
to
dive
down
into
the
spice
level
representation
and
simulate
it
and
then
annotate
that
dynamically
back
into
the
gate
level.
But
that's
a
further.
A
B
Yeah
interesting
yeah
rob
I'm.
I'm
gonna
follow
up
with
you
on
that,
because
that's
something
yeah,
I'm
curious.
If
you
you
know,
we've
been
looking
at
ways.
Is
there
a
way
to
like
basically
cut
some
wires,
generate
an
entire
gds,
but
then
just
cut
some
wires
and
do
post
packs
on
just
the
part
I
snipped
out
and
simulate
that
right.
B
You
know,
but
don't
I
don't
want
to
simulate.
You
know
all
the
digital.
I
just
want
to
simulate
part
of
it
part
of
my
circuit.
It
doesn't
include
the
digital
so
to
speed
it
up,
but
we've
not
been
successful
at
finding
a
way
to
like
find
the
design
first
of
all
and
then
cut
it
out
and
just
simulate
it.
So
if
yeah,
that's
I'm
interested
in
that.
Okay,
if
you've
been
able
to
do
the
like
the
clock
net,
it's
kind
of
the
same
thing.
You
know
it's
carving
out
the
design
yeah.
C
And
by
the
way,
just
while
we're
mentioning
that,
I
I
don't
know
if
people
are
aware
or
not
so,
we've
been
involved
and
we
had
worked
and
used
some
setups
for
mixed
mode
simulation.
Mixed
simulator
simulation,
like
I
verilog,
with
ng
spice
together
running
a
mixed
mode
design.
It's
not.
This
is
just
a
simulation
aspect.
C
Is
that
I'm
trying
to
actually
put
an
application
note
about
this,
because
it's
becoming
an
issue
in
a
google
slash
of
sky
water
in
general?
Okay,
and
we
we
we've
done
a
couple
of
tricks
and
we
did
it
on
a
ship
like
raven
so
anyway,
so
it
doesn't
solve
your
problem
by
selecting
one
net
extract
it
and
go
through
it
yeah,
and
I
I
bet
you
there
will
be.
C
You
know
I
mean
I
know
back
20
years
ago
or
at
least
yeah
20
years
ago,
when
I
was
working
back
on
cadence
and
things
like
that
they
were,
there
was
a
you
know:
selection
selector
net
to
be
extracted,
but
it
always
it
always
decouples
the
caps
to
ground,
for
example,
instead
of
the
right
neighboring
name.
You
know.
C
B
A
F
F
H
F
B
B
Other
applications
of
this
same
thing
as
well,
but
I'd
say
one
of
the
cool
things
that
you
can
do
when
you've
when
you,
basically
when
you
have
access
to
kind
of
this
methodology,
is
like
look
at
other
ways
to
get.
In
this
case
we
looked
at
fine
delay,
control
of
the
oscillator
or
fine
frequency
control
using
pulse
width
modulation
so,
rather
than
driving
the
control
signals,
as
always
on
or
always
off,
for
a
tri-state
buffer,
we
would
pulse
with
modulate
those
control
signals
at
the
clock,
frequency
at
the
high
clock
frequency.
B
So
instead
of
you
know,
you'd
get
a
let's
say
it's
a
one,
gigahertz
oscillator!
We
would
have
a
pulse
that
every
every
clock
cycle,
every
one
gigahertz,
every
one
nanosecond
you
get
a
pulse
and
we'd-
be
able
to
modulate
the
width
of
that
pulse,
using
a
cell-based
circuit
that
produces
a
pwm
block
and
by
by
just
pulsing
the
or
controlling
the
width
of
the
enables
of
the
buffers
you
get
much
finer
control
over
that
edge.
You
know,
think
of
falling
edge
or
a
rising
edge.
B
You
can
just
barely
tweak
that
edge
with
a
little
bit
stronger
buffer
just
for
a
small
period
of
time
and
you
shut
it
back
off,
and
so
you
can
barely
tweak
the
edge.
You
can
get
very
fine
control,
and
this
this
gave
us
actually
a
huge
improvement
in
resolution
which,
in
an
all
digital
pll.
That
means
you
know:
lower
noise,
lower,
spurs
everywhere
so
gave
us
much
better
performance,
and
actually
this
is
the
first
cell-based
pll
that
we
used
in
a
radio.
I
think
we
use
this.
B
I
think
we
did
a
400
megahertz,
med
radio.
You
know
a
body
area
network
w
band
radio
with
this,
but
this
is
the
first
time
that
we
used
a
ring
oscillator.
That
was
automatically
generated
for
a
radio
meaning
the
phase.
Noise
performance
is
good
enough
for
radio.
So
all
right,
so
that's
pwm.
So
that's
kind
of
an
aside.
You
know
if
you
look
at
individual
stage.
It'll
have
tri-state
buffers
strong,
tri-state
buffers,
weak,
tri-state,
buffer
and
switch
caps.
So
there
were
three
auxiliary
cells
that
we
built
for
this
pll
each
cell.
B
You
would
then
lay
out
on
the
standard
cell
grid.
Today
we
are
using
a
line
to
automate
the
layout
of
aux
cells.
We've
actually
been
going
back
and
forth
the
past
three
weeks
to
implement.
We
have
five
cells
now
implemented.
Five
of
our
aux
cells
in
fa
sock
are
automatically
laid
out
using
the
align
tool
in
gf12,
so
we're
working
on
expanding
that
to
the
rest
of
the
cells.
But
I
you
know
we
can
automate
the
layout
of
these
standard
cells
as
well,
and
then
this
is
a
question.
C
B
B
B
B
Yeah,
okay,
so
then,
once
you
have
the
cells
laid
out,
then
you
can
do
things
like
build
a
single
stage
macro
where
I'm
gonna
for
one
stage,
I'm
gonna
take
all
these
cells
and
I'm
gonna
place
them
in
a
macro
so
that
when
I,
when
I
drop
down,
let's
say
five
stages,
each
stage
looks
the
same.
It's
using
the
same
macro.
So
then
I
can
drop
down
stage
macros
to
assemble
a
full
dco
connected
in
a
loop
and
then
apr
the
whole
thing.
B
So
the
the
only
custom
layout
at
this
point
is
just
to
generate
those
three
aux
cells.
That's
a
one-time,
porting
cost!
After
that,
you
can
scale.
Number
of
you
know
buffers
per
stage,
caps
per
stage
number
of
stages
to
get
a
wide
range
of
different
dcos
from
this
all
generated,
and
you
know
apr
using
the
digital
flow
at
that
point.
B
So
here's
what
it
looks
like
in
gf12-
and
this
is
this-
is
now
using
python
scripts
to
structure
the
placement
of
fine
and
coarse
cells,
notice
stage
zero
stage
one.
So
a
stage
goes
across
the
top,
so
stage
is,
is
short
and
fat
in
this
layout
notice.
The
structure
of
the
aux
cells,
but
then
that
dco
sits
right
here
in
the
middle
of
the
rest
of
the
pll,
which
is
all
apr'd,
so
the
rest
of
pll
is
all
apr
and
then
we
surround
it
with
decoupling
capacitors.
A
B
H
B
B
B
I
B
A
timeline
to
get
the
cadre
flow
I'd
have
to
ask
ron
that
question.
I
don't
think
I
think
right
now.
The
plan
andrew,
because
we're
doing
open
road-
and
I
think,
right
now,
the
plan
is
to
stand
it
up
outside
of
cadre
and
I
think
that's
what
many
has
done
for
his
take
out.
That's
so
when
those
two
things
converge
really
comes
down
to
when
ron's
gonna
throw
some
resources
on
that,
and
I
don't
have
a
good
answer
for
that,
meaning
if
you
know
it's,
it's
not
it's
not
in
the
next
couple
quarters.
I
B
Yeah
another
example
ldo
for
power
regulation.
The
schematic
shown
here
down
in
the
right
very
simple,
ldo,
with
a
pmos
switch
and
controller,
and
then
some
kind
of
comparator
we've
implemented
a
few
different
versions
of
that
comparator,
all
cell
based
so
here
just
showing
what
it
looks
like
pre-pex
simulation
of
you
know
max
load,
current
versus
the
size
of
the
array,
and
then
once
you
run
it
through
apr
and
just
randomize
things,
you
kind
of
what
happens
to
that
max
load
current.
B
B
So
we
we,
you
know,
apply
some
tricks
here
on
the
left
to
cut
down
on
the
loss,
resistance
using
again
non-default
rules,
and
then
we
use
some
more
structured
placement
of
those
cells
to
get
more
regular
placement
with
the
apr
engine,
and
we
can
get
that
nice
relatively
smooth
curves
back
and
we
get
the
load
current
back
up
to
where
we
wanted
it.
So
just
an
example
of
all
right:
if
you
just
give
it
to
the
tool,
you
know
and
let
the
tool
do
its
thing,
you
probably
won't
get
what
you
want.
B
B
Medi
has
been
working
on
our
adc,
we've
built
a
sar
adc,
so
here's
you
can
see
a
smack
at
the
top.
We
put
a
couple
adcs
down
in
our
last
chip,
and
here
you
can
see.
Medi
has
been
playing
around
with
some
common
centroid
placement
again
using
using
script
placement
of
the
cells,
but
can
do
things
like
common
centroid
layout
in
a
scripted
way
and
make
it
parameterized
make
it
scalable.
B
In
our
our
last
gf12
chop,
we
we
also
dropped
down
a
bluetooth
transmitter,
so
complete
radio,
including
gfsk
modulator,
gaussian
frequency,
shift
keen
that's
what
bluetooth
uses
to
communicate
a
pll,
a
ring-based
pll
to
generate
the
lo
signal,
ldo
to
drive
the
power
and
we
use
the
switch
cap
pa
the
switch
cap
pa
was
custom.
This
is
the
only
thing
that
was
custom
laid
out
in
this
design.
Everything
else
was
run
through
our
generators
and
and
flow.
B
We
are
now
looking
at
making
a
cell-based
version
of
the
switch
cap
pa
in
order
to
make
that
synthesizable
as
well.
That's
one
of
the
new
blocks
that
I
was
talking
about,
we're
adding
all
right
so
pulling
that
all
the
back
together
to
the
top
level
flow
chart.
You
know
we've
been
talking
about
the
basically
this
this
bottom
part
here
about
generating
analog
blocks.
B
B
We
populate
a
cots
library
from
those
analog
generators,
but
we've
also
built
this
data
sheet
scrubber.
That
can
just
look
at
a
pdf
like
a
conference
publication
or
a
data
sheet
and
can
pull
out
some
specs
and
put
that
into
a
library
to
help
inform
the
soc
on
kind
of
what's
possible
and
then
our
soc
gets
trained.
B
We
have
models
for
the
soc
that
help
take
user
specs
and
then
choose
what
to
pull
from
these
libraries
in
order
to
build
that
full
soc
we've
built
a
couple
of
those
today,
one
in
65,
one
in
gf12.
I
intentionally
drew
these
to
scale.
I
shrunk
this
guy
so
they're
to
scale,
and
the
thing
I'll
point
out
here
is
the
ldos
from
65
to
12
got
smaller
the
plls
from
65
to
12
got
smaller.
B
The
memory
got
smaller,
but
that's
not
probably
not
a
surprise
to
everybody,
but
you
know
the
how
how
many
times
can
you
say
you
know
when
you
port
an
analog
block
from
from
you
know
to
a
more
advanced
node.
It
gets
smaller
right,
that's
pretty
rare,
I
think,
and
so
because
we
adopt
this
cell-based
approach.
We
use.
You
know
things
that
mimic
the
standard
cell,
library
and
digital
cells.
B
A
couple
more
slides
one.
I
asked
all
the
students
to
measure
the
time
it
took
to
port
from
65
to
12,
and
this
is
what
they
reported.
The
cadre
setup
took
about
two
weeks:
that's
that's
our
digital
flow,
so
we
had
to
set
our
digital
flow
up
and
that
took
about
two
weeks.
But
then,
if
you
look,
every
generator
took
on
average
about
two
weeks
the
sram
took
a
little
longer,
but
everything
else
took
about
two
weeks
to
these.
B
B
A
F
And
thanks
rob
for
the
idea
right,
you
kind
of
you.
You
came
up
with
the
idea
of
having
presentations.
I
think
it's
it's
a
great
way
to
get
products
introduced.
I
think
like
this
is
awesome,
david
and
maddie.
I
think
the
most
important
kind
of
question-
that's
in
front
of
us
in
a
sense,
is
how
do
we,
you
know
enable
fa
stock
to
kind
of
go
towards
you,
know
commercial
use
and
and
kind
of
using
projects
that
either
otherwise
wouldn't
be
possible.
F
And
how
can
we
help
like
not
just
we
don't
just
want
you
to
kind
of
come
and
present,
and
we
all
nod
our
heads
and
yeah
appreciate
the
great
work
but
more
like
how
do
we
kind
of
plug
more
people
into
the
effort
we
have
more
brains
here
and
that
can
potentially
assist
and
more
people
working
up
with
other
open
source
projects.
Martin.
D
F
D
G
B
F
B
Yeah
mike,
I
was
gonna,
come
back
to
your
question,
so
so
you
know
you
mentioned,
like
commercial
use,
you
know
how
do
we?
Basically?
How
do
we
drive
that
and
then
how
do
we
plug
into
existing
open
source
so
on
the
commercial
use
side
the
way
so
I've
had
I've?
Had
students
do
internships?
I
know
that's
not
the
answer
you
want
to
hear,
but
that's
one
way
that
we
have
we've
gotten.
These
tools
stood
up
at
other
companies.
B
If
that's
what
you
mean
by
commercial
use-
and
you
know
that
includes-
I
mentioned
cadmium
networks,
but
also
intel
and
motorola
afrl
to
name
a
few.
Those
are
the.
I
think
those
are
the
four
where
we've
stood
up.
We've
had
interns,
students
go
and
specifically
do
interns
to
stand
up
the
tools,
so
so
that
is
one
way
to
certainly
do
it,
but
and
that's
that
is
because,
when
you
go
into
a
company,
they're
gonna
have
their
own
tools,
their
own
tool
flow
right,
their
own
pdk.
B
If
you're
intel-
and
you
know-
we
can't
see
that,
and
so
you,
you
kind
of-
have
to
stand
things
up
there
in
their
design
environment.
So
I
am
certainly
open,
I'm
not
a
tools
guy,
so
I
am
open
to
ideas
there
on
how
to
make
these
things
more
portable.
I
know
there's
a
lot
of
tools,
people
on
the
call
so
so.
C
C
C
They
won't
believe
in
that
my
view
of
that
is
that
show
their
specs
yeah
people.
Listen,
I'm
sure
the
text
and
the
slide
about
timeline.
Because
that's
how
I
argue
I
didn't
argue
this
is
how
I
made
the
point
to
ti
you,
you
design
for
spec
through
the
same
specs
or
better
or
first
time
success
and
then
challenge
and
say:
okay,
well,
we're
doing
this
and
we're
doing
it
shorter
than
time
than
the
other
guys.
So
there's
something
to
be
learned
there
and
then
they
start.
C
Everybody
wants
to
look
good,
wants
to
be
productive,
not
just
ego,
so
they
once
they
see
results
and
in
a
good
timeline.
They
say
I
want
to
do
this
yeah,
so
I
think,
having
a
published
results
and
measured
and
in
a
good
methodology
and
good
characterization
around
it,
it
will
actually
go
a
long
way
to
pull
the
tool.
In
that's
my
view,.
B
C
Like
serenova
the
company
back
when
it
they
would
go,
sell
it
to
analog
analog
analog
and
ended
up
intel.
You
know
was
getting
it
because
they
they
wanted
some
sort
of
automation
around
certain
things
that
they
didn't
want
to
have.
They
need
them,
codified
knowledge,
codified
knowledge
for
that,
so
yeah
yeah
just
make
it
on
sky
water,
and
I
guarantee
you
it's
going
to
take
its
own.
C
E
C
C
No
I'm-
and
this
is
not
on
your
end-
I'm
saying
I'm
talking
about
docker
container.
Okay,
I
don't
care
about
any
other
thing.
I
I
want
something
that,
in
within
five
minutes,
somebody's
up
and
running
no
question,
so
I'm
not
telling
you
to
do
it.
I'm
just
saying
I'm
because
I
know
there
are
so
many
constraints
about
that,
but
the
idea
is
to
make
it
easily
usable,
so
people
can
evaluate
it
and
see
the
results
that
also
it
changes
the
dynamic
of
how
fast
that
can
move
forward.
B
C
C
C
Put
that
container,
it's
called
simplicity.
The
way
I
call
it
and
it
has
you
can
log
in
you
can
run
the
container
and
it
opens
a
session
for
you.
You
can
just
become
run,
run
spice
run.
You
know
digital
flows
around,
so
I
would
like
to
add.
You
know
once
it's
once
I
get
to
it
or
somebody
would
get
to
it.
I
would
add
that
into
the
container
and-
and
I
can
show
it
to
you
and
maybe
that
would
become
a
just
another-
build
another
part
of
the
build.
C
F
C
B
Yeah
yeah
actually
muhammad,
I
so
you
bring
up
a
good
point,
so
I
would
say
you
know
when
I
think
about
setup.
I
think
about
all
the
work
that
you
did
behind
the
scenes
to
make
it
so
that
somebody
can
just
get
set
up
in
five
minutes.
But
when
you're
thinking
set
up
you're
thinking,
someone
comes
to
your
environment
and
now,
once
they're
in
your
environment,
they
can
get
set
up.
So
I'll.
B
C
C
B
C
Yeah,
so
I
wonder
I
I
I
maybe
I'm
sorry
to
open
the
topic,
but
I
but
it's
important,
so
you
know
I'd
like
the
tools
that
are
coming
out
of
this
program.
This
group,
as
well
many
things
like
I
saw
a
couple
of
people
on
slack
they're,
saying
I'm
trying
bag
and
I'm
trying
a
line
and
then
well
so
there's
magical.
So
I
am
trying
to
say
to
people
as
long
as
much
as
you
did.
You
brought
you
promote
the
tool
and
its
capabilities
for
design
output.
C
It
is
actually
key
to
make
it
easily
accessible
by
someone
without
even
the
emotional
barrier.
So
I'm
not
saying
you
do
it
again.
I
think
we
have
a
process
that
can
include
this.
We
actually
have
a
docker
container
that,
like
a
docker
file,
that
you
can
specify
what
you
need
and
then
we'll
just
rebuild
that
thing
anytime
and
add
to
it
lines
as
much
as
you
want.
So,
as
I
said,
I'm
just
in
the
process
of
making
that
available
as
an
open
thing,
so
that
we
don't
become
the
only
people
to
maintain
it.
F
Okay,
thank
you
we're
running
out
of
time
and
we
won't
be
able
to
push
over
7pm
andrew
already
had
to
to
to
drop
so
sorry
7pm
for
me
obviously
kind
of
early
in
the
day.
For
most
of
you
probably
anyhow,
we
have
a
bunch
of
things
that
we
didn't
manage
to
do
today
and
I
think
it's
fine.
I
don't
think
we
really
need
to.
We
can
kind
of
continue
over
email.
Remember,
there's
a
mailing
list.
We
should
definitely
start
like
exchanging
emails,
not
just
meeting.
F
We
have,
by
the
way
the
align
framework
is,
is
kind
of
reaching
out
to
join
us
as
well,
so
hopefully
great
we
can
get
projects
in
faster
than
we
can
kind
of
run
out
of
presentations
to
to
cover
and
obviously
won't
be
able
to
do
that,
but
let's
at
least
try
to
to
keep
this
up
for
a
little
while
and
then
let's,
let's
continue
next
time
with
the
presentation
two
weeks,
I
think
it's
a
good
cadence
to
to
run
fairly
fast,
but
not
too
fast.
I
mean
everyone's
busy.
F
So
I
guess
we'll
try
to
find
a
slot
two
weeks
from
now.
I
don't
know
if
tuesday
is
acceptable,
actually
because
we
started
off
on
a
tuesday
and
we
exceptionally
moved
this
to
to
monday
this
week.
But
I
don't
know
if
tuesday
works
or
should
we
send
a
doodle
out
now
that
we
have
a
bunch
of
people,
I
think
perhaps
a
doodle
is
in
order.
Yes,.