►
Description
Presentation by Dan Fritchman of UC Berkeley
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C
So
that'll
be
a
good
chunk
of
the
talk
in
progress
test
trip.
You
know,
that's
where
a
lot
of
my
background
is
and
that
sort
of
intersects
with
a
couple
of
other
threads
going
on
here.
So
we
thought
that
would
be
a
good
combo
project
for
a
lot
of
the
software
on
the
show,
the
next
hour
and
the
open
source
pdk
and
the
backgrounds
of
some
of
the
folks
we
have
available
here.
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F
B
Cool
so
thanks,
everyone
for
joining
and
first
I
would
like
to
apologize
for
last
week.
I
was
having
some
health
issues.
I
feel
I'm,
feeling
much
better
right
now
and
I'm
really
excited
about
the
talk
from
Dan
Richmond
from
UC
Berkeley,
who
will
present
the
design
of
an
open
source
USB
file
using
a
couple
tools.
B
One
of
them
is
the
python-based
analog
htl,
which
I'm
pretty
interested
in,
and
it's
paired
with
the
schematic
system.
So
we'll
I'm
looking
forward
here
in
more
details
about
that
and
he's
using
a
couple.
Other
tools
like
real
estate
are,
and
they
have
to
programming
with
lab21
GTS
21
and
left
21.,
so
danf
Richmond.
Please
share
your
screen
and
tell
us
more
about
your
work.
Yeah.
C
Thanks
Manny
and
just
to
maybe
correct,
just
maybe
set
expectations
a
little
bit.
We
are
going
to
focus
a
bit
more
on
the
latter
half
of
what
you
just
said.
So
all
the
software
behind
this
is
the
presentation
coming
through
yep,
okay,
great
so
I'm
going
to
talk
about
along
with
the
stuff,
and
then
he
just
Ravel
off.
In
fact,
we're
probably
not
going
to
cover
all
this.
We
need
probably
three
quarters
of
it
in
an
hour.
C
In
a
brief
historical
view
of
that
project,
that
motivates
some
of
our
work
that
history,
I,
think
of
in
a
few
eras,
so
kind
of
prehistory
in
a
sense
is
the
circuit
researchers
here
at
Berkeley,
do
like
everybody
else.
Click
around
Cadence
is
virtuoso.
Draw
schematics
draw
layouts
as
such,
and
eventually
some
smart
grad
students
and
professors
realize
we
do
a
lot
of
this
similar
stuff
over
and
over
again,
it
is
amenable
to
being
programmed.
C
We
have
programs
that
figure
out
how
to
design
these
circuits
at
higher
levels
and
put
together
bag,
which
is
in
a
view,
a
python
library
that
writes
skill
code,
hands
it
to
virtuoso.
Has
that
evaluated
to
manipulate
schematics,
layouts
and
the
like,
and
that
produced
a
lot
of
great
research?
We
got
a
lot
of
good
takeouts
out
of
it.
Is
there
a
kind
of
a
lag
between
what
you
guys
see
and
what
I'm
saying.
C
C
C
The
virtuoso
gets
really
slow
and
makes
a
very
faithful
decision,
which
is
si2
offers
a
c
plus
API
to
the
underlying
data
model,
called
Open
Access,
if
you're
a
member
of
si2
and
can
get
access
to
it,
and
so
the
project
transitions
to
using
this
very
directly
and
very
comprehensively
big
problem
ensues,
which
is
that
we
then
lose
that
license.
It's
been
gone
now
the
entirety
of
the
time
that
I've
been
here,
which
is
over
three
years
now,
and
while
it's.
G
C
Only
factor
it's
a
material
factor
in
the
fact
that
development
in
that
projects
really
stopped
here
right.
It's
also
been
impacted
by
the
fact
that
the
sort
of
original
designers,
both
amongst
the
grad
student
researchers
and
key
Professor,
have
all
left,
but
an
important
fact
is:
we
can't
write
this.
We
can't
even
compile
it
in
fact,
so
we
have
a
few
users
left,
but
with
this
gone
pretty
much
back
to
that
prehistory
right,
the
way
back
to
now
is
kind
of
what
everybody
else
does.
C
So
the
first
lesson
of
this
to
me
at
least,
is
don't.
Do
that
again?
Okay,
don't
get
stuck
in
this
situation
for
some
Central
building
block
I
should
have
added
at
the
beginning
by
the
way
I
encourage
you
to
interrupt.
I,
probably
won't
see
the
hand
thing
so
just
interrupt
me
and
talk
and
I'll
answer
questions
Midway
through.
C
So
first
question
is:
what
is
this
thing
that
we
got
licensed
out
of
what
is
in
these?
What
is
in
these
design
databases,
or
at
least
this
one
in
particular
and
at
bottom?
This
is
a
binary
data
format
and,
in
a
ways
case,
the
C
plus
plus
API,
to
manipulate
it.
So
do
things
like
add
a
polygon
to
a
layout,
get
all
the
instances
in
a
schematic.
Some
notion
of
linkages
between
these
things
and
the
the
message
here
is
they're
not
made
of
magic
right.
C
This
one
does
have
a
magic
facet,
which
is
that
it
is
the
format
for
the
most
popular.
You
know:
design
environment,
but
they're,
not
in
principle
the
hard
part
and
so
I've
introduced
one
of
our
project,
snacks,
which
is
called
blcir
or
design
databases.
Protocol
buffers,
so
I'll
introduce
protobuf
first
I
know
depending
what
audience
I'm
in
there's
more
or
less
familiarity
with
that
project.
C
The
idea
there,
the
goals
there
kind
of
start
with
the
Advent
of
the
cloud
hyperscaler
companies,
and
so
if
you
have
tens
of
thousands
of
Engineers
hundreds
of
projects,
hundreds
of
kind
of
server-side
programs
that
need
to
communicate
with
each
other
to
do
things
like
the
largest
web
scale.
Companies
do
now
most
have
reached
an
acknowledgment
that
there's
just
no
practical
way
to
get
all
of
those
Engineers
on
the
same
page.
C
Think
of
this,
as
if
you
can
write
a
c
program,
but
you
can
only
Define
structs,
that's
it
and
the
struct
type
is
called
message
which
is
sort
of
indicative
of
it
being
designed
for
communication
between
these
programs,
but
the
gist
of
using
this.
Is
you
write
this
schema
data
model
and
then
run
this
compiler
that
produces
code
in
kind
of
any
language
you'd
like
like
every
popular
language
that
would
use
it
and
then
exchange
between
programs
in
those
languages
all
right.
So
this
is
an
important
motivating
project,
Captain,
Proto,
flat
and
flex.
C
Buffers
are
similar
ones
that
are
all
all
share
these
traits
I'm
talking
about
here.
That
I
think
are
quite
valuable
to
our
problem.
There's
another
project
I'll
introduced-
and
this
is
cited
by
a
lot
of
icy
industry
projects
of
late
I.
Tell
the
lbm
and
the
particular
component
or
particular
facet
to
highlight-
is
this
breaking
of
that
project
into
these
three
layers.
So
llbm
is
the
compiler
infrastructure.
C
So
the
goal
here
is,
if
you
are
going
to
change,
say
the
front
end
for
rust
or
the
back
end
for
x86.
It
doesn't
necessarily
screw
with
everything
else
right
there
is
this
modularity
in
this
capacity
to
exchange
this
thing
in
the
middle.
Thank
you.
So
those
two
pictures
in
mind
our
vlsir
system
looks
a
little
bit
like
each
of
them.
C
There's
a
protobus
schema
called
the
sir
and
a
paired
that
the
ideas
that
are
captured
in
that
data
schema
are
circuits,
layout
and
kind
of
spice
class
analog
simulation
today,
The
Interchange,
so
that
serves
as
the
middle
layer
of
something
analogous
to
the
prior
picture.
The
Interchange
is
on
the
front
end.
C
We
we
use
various
or
label
here
has
fancy
front
ends
so
kind
of
nice
programming
interfaces
to
do
stuff
to
this
vlsir
data
model.
So
we're
going
to
look
at
Several
of
these
fancy
front
ends
over
the
course
of
this
presentation,
but
in
these
different
programming
languages
that
the
protobuf,
compiler
or
compiler
is
support.
Write
code
to
manipulate
circuits,
manipulate
layout,
run
and
Par
simulations
and
the
like
and
on
the
back
end,
are
really
the
industry
standard
formats.
So
many
of
the
projects
Maddie
cited
in
introduction,
there's
one
key.
C
So
there's
a
handful
is
all
relatively
new,
but
there's
a
handful
of
ongoing
projects
here,
there's
a
sky
130,
s3m
compiler
in
the
works
that
I
know
has
gotten
a
good
amount
of
attention
by
the
community
working
in
the
open
source
technology.
Similarly
researcher
here
our
Irish
Parsi
working
on
fpga
compiler,
those
are
both
kind
of
structured,
digitally
looking
circuits,
whereas
the
rest
of
this
list
is
very
analog.
C
So
what's
in
these
things
can
I
come
back
to
this?
It's
not
rocket
science.
This
isn't.
The
hard
part
of
our
job
is
what
is
in
the
this
data.
This
is
not
exactly
wsir
schema,
but
it
is
reflective
of
it
right.
This
is
not
in
protobuf
syntax.
In
fact
it's
in
pythons,
but
what's
in
a
layout
at
bottom,
is
two
things.
One
are
geometric
elements:
shapes
2D
shapes
that
have
a
3D
layer
affixed
and
instances
of
other
layouts
right.
C
So
this
isn't
the
literal
bsir
schema
but
really
does
convey
the
idea
of
what's
behind
it
now
there's
another
type
of
thing
in
this
big
picture
space
that
I
want
to
introduce
to
motivate
one
of
those
front
ends
and
we'll
we'll
get
there
through
a
little
thought
experiment
which
is
basically
a
test
of
how
well
we
could
we
understand
what
these
things
are
ourselves
and
I.
Think,
oh,
it's
a
dinner
party
test.
C
It's
really
how
well
how
well
could
you
describe
what
this
thing
is
to
someone
not
in
your
field,
all
right
so
I'll
do
a
couple
of
examples
if,
let's
say
I'm
explaining
to
someone
who's
smart,
but
not
an
engineer,
maybe
they're
a
doctor
or
lawyer
like
what
is
this
thing
on
screen
I
think
I.
Do
that
pretty
effectively
right,
it's
kind
of
a
list
of
instructions
for
the
computer
to
do
it
goes
top
to
bottom.
C
It
does
the
first
thing
it
does
the
second
thing
there
are
some
special
ones
that
say
jump
to
here
or
jump
to
there
or
keep
doing
this.
They
probably
largely
get
it
second
test.
I
also
think
I
can
explain
pretty
well
what's
this.
This
is
a
blueprint
right.
This
is
the
physical
Design.
This
is
the
physical
fabrication
instructions
for
a
chunk
of
a
chip.
C
The
X
and
Y
axis
are
stuff
to
sort
of
shoot
at
a
silicon.
Wafer
and
the
colors
are
sort
of
z-axis
markers
right.
Different
colors
reflects
sort
of
different
depths
in
and
out
of
the
screen
in
this
sort
of
Two
and
a
Half
D
View,
the
one
that
I
think
is
much
harder,
and
you
know
honestly
on
some
level.
I,
don't
know
what
this
is
now.
C
As
a
practitioner,
I
obviously
do
like
I
said:
I
come
to
this
as
an
analog
designer
and
in
some
sense
my
career
is
made
of
these
things,
but
like
as
a
person,
I
really
am
not
sure,
I
know
what
is
it
and
clearly
it's
a
schematic,
but
why
these
little
squiggles
have
such
significance
to
me
and
to
everyone
else
in
our
field.
I'm,
not
sure
that
I
can
explain
so
and
that's
even
for
this
is
a
good
schematic
right.
C
C
Two
giant
rectangles
with
500
pins
in
between
them.
If
we
zoom
in
on
them,
no
one
has
ever
been
willing
to
name
the
instances
in
them,
except
for
the
default
value.
Most
of
the
signal
names
have
about
five
underscores
in
between
them
that
are
essentially
making
hierarchical
sub
references
into
one
another.
C
C
That
is
not
that
much
worse
than
actual
circuits
that
are
actually
out
there
in
the
world
better.
Yet
we
zoom
in
on
some
of
the
connections
between
these.
They
each
have
ports
named
who?
What,
when,
where
and
why
and
there's
a
note
now,
this
is
actually
better
in
a
sense
than
a
lot
of
industrial
schematics.
C
There
at
least,
is
the
note,
but
what
the
note
says
is
internally,
who
connects
to
what
and
when
what
connects
to
who,
where
connects
to
when
and
when,
where
is
high,
what
is
disabled
and
who
reroutes
to
where,
which
is
you
know,
kind
of
an
avid
Costello
routine
mock
comment?
But
it's
honestly
not
that
much
worse
than
a
lot
of
real
life
ones,
so
I
think
there's
a
couple
of
reasons
why
we
have
so
many
of
these
just
really
bad
ways
of
describing
these
circuits
of
Designing.
C
These
circuits
there's
no
argument
that
this
is
that
this
picture
is
like
the
best
way
of
stating
the
content
of
this
thing
or
designing
it.
That
I
can
see
the
reason
that
they're
there
is
because
they're
sort
of
in
tuned
with
other
schematics
that
are
battery
and
I.
Think
if
we
can
break
that
up,
we
can
do
a
lot
better
in
this
space
and
that's
kind
of
what
motivate
a
lot
of
what
motivates
the
first
of
those
fancy
front
ends
I'm
going
to
show
it's
a
project
called
hdl21.
C
This
is
an
analog
HDL
based
in
Python.
The
goals
here
are,
first
and
foremost,
this
is
for
to
be
for
circuit
designers.
This
is
a
group
of
people
who
has
a
lot
of
specialized
knowledge.
We've
talked
in
this
meeting
in
the
past
about
some
threshold
slopes
and
how
they
impact
certain
classes
of
circuits.
We'll
talk
about
you
know:
phase
noise
of
oscillators
later
in
this
presentation.
C
There's
this
is
a
group
of
people
who
has
a
lot
of
hard-won
knowledge
that
it's
easy
to
lose
track
of
in
a
form
like
this,
but
a
lot
of
programming
is
not
necessarily
part
of
it
and
even
I
would
say,
usually
not
part
of
it.
So
the
idea
behind
this
library
is
to
expose
the
ideas
that
the
people
with
the
net
requisite
knowledge
to
make
the
circuits
are
comfortable
with
in
the
most
comfortable
programming,
environment
and
I.
C
Think
python
is
the
best
language
for
that
as
commonly
recognized
as
sort
of
the
most
accessible
and
perhaps
more
importantly,
the
place
where
most
of
the
other
stuff
they
would
want
to
do
is
going
to
happen.
So
data
analysis
is
a
great
example.
If
you
want
to
get
a
machine
learning,
it's
sort
of
the
hub
for
that,
and
so
the.
C
So
what
is
in
that
space
modules
are
very
essential
element
generators,
which
is
a
term
we
use
here
at
Berkeley.
A
lot
are
a
first
class
term
here,
an
important
one
and
then
all
of
the
other
stuff.
That's
only
the
sort
of
analog
tribe
needs
and
uses
interacting
with
spiced
plant
stimulation
process,
Technologies
our
first
class
things
and
our
hip
installable
python
packages,
Corners
all
of
the
stuff
that
you
need
to
perform
the
task
of
Designing.
C
These
you
know
circuits,
so
the
first
major
idea,
kind
of
the
thing
that
hdl121
circuits
are
made
of
in
a
sense
is
its
module.
Module
is,
hopefully
feels
comfortable
as
a
term
and
what
you're
used
to
that
term,
meaning
so
the
way
you
generally
make
these
is:
stick
a
little
module
widget
on
top
of
a
class
definition
and
then
to
clear
its
content,
which
generally
consists
of
ports,
signals
instances
of
other
modules
connections
there
between.
C
C
You
know
a
lot
of
people
we're
going
to
see
just
the
role
of
like
functions
in
this
context
very
shortly,
and
even
that
is
not
a
level
that
I'm
presuming
people
care
to
program
at
right.
So
the
very
next
slide
includes
the
sort
of
right.
Half
of
the
slide
is,
if
you
want
to
produce
hardware
and
kind
of,
let's
call
it
Matlab
script
context
right
just
running
beginning
to
end
as
long
as
you're
comfortable,
making
a
variable
here
called
B2
and
sticking
stuff
onto
it.
You
can
make
these
modules
perfect.
C
C
The
kind
of
second,
the
other,
really
big
picture
thing
is
the
generator.
We
use
that
term
here
at
Berkeley
to
mean
all
kinds
of
different
stuff.
Here
it
is
the
proper
noun
which
means
is
a
function
of
some
parameters.
It
returns
one
of
those
modules,
that's
it
if
you're
comfortable,
writing
that
you
can
make
generators.
Now,
it's
not
any
function
that
can
do
that.
There
are
some
constraints
on
them.
Generally
stick
another
little
widget
on
top
of
a
function.
Definition
is
the
mechanism.
C
This
does
some
helpful
things
in
the
background,
and
there
are
some
constraints
we'll
see
on
the
arguments
to
this
thing.
The
parameters,
but
the
important
thing
to
note
is
the
program
is
dictating
the
entire
content
of
the
circuit
here
right.
So
in
our
example,
we
create
a
module.
We
create
an
input
which
has
a
parametric
width
and
then
also
parametrically.
C
You
know,
depending
on
arguments,
to
take
the
content
right
if
the
parameters
say
to
include
the
reset
input
in
this
example
included,
if
they
don't
so
that
can
do
things
like
swap
in
and
out
architectures
of
entire
subsystems
or
just
to
kind
of
simple
numeric
things
like
change.
The
width
of
an
array.
C
Now
this
is
where
we
get
the
parameters
or
where
we
get
to
some
of
the
forced
organization
and
well.
This
is
not
from
a
bag
generator
or
even
a
circuit
program.
This
is
kind
of
reflective
of
certainly
among
grad
students,
so
I
get
to
spend
a
lot
of
time
with
now,
but
also
among
attempts
to
program
this
kind
of
stuff.
What
things
often
look
like
this
is
from
a
machine
learning
project.
It's
a
c
function
that
I
believe
has
21
arguments,
many
of
which
are
parametricized
in
and
of
themselves,
it's
static,
so
there's
internal
state.
C
So
don't
do.
This
is
one
of
the
next
goals
and
the
generator
parameters
have
a
couple
of
mechanisms,
or
probably
a
half
dozen
things
to
point
out
about
them
to
help
avoid
that
the
first
is
they're
organized
as
a
type
so
they're
they
have
to
get
rolled
into
one
thing:
it
gets
another
little
decorator,
widget
called
the
param
class
on
it
to
make
it
so
they
the
generators,
only
work
with
something
that
is
kind
of
aggregated
up
into
a
type
like
this.
C
Second,
they
all
are
at
least
at
sort
of
definition
time.
This
param
thing,
which
includes
a
couple
of
important
Fields
one,
is
a
required
data
type.
Those
all
get
type
checked
at
runtime.
This
is
another
often
kind
of
hot
debate.
Here.
Are
these
strongly
versus
weekly,
typed
languages
and
and
python
is
great
for
getting
rolling
it
also
can
be.
C
It
also
can
sort
of
roll
up
to
be
a
problem
in
bigger
projects,
and
particularly
not
especially
well
documented,
bigger
projects
to
have
this
kind
of
free
form
types
of
everything.
This
library
takes
the
approach
of
injecting
the
type
safety
at
runtime.
So
all
of
these
parameters
are
certainly
typed.
They'll
have
a
required
description,
and
if
they
are
going
to
be
optional,
if
you're
going
to
get
a
default
value,
then
they
provided
one
so
the
to
do
a
few
more
things,
so
they
nest.
The
example
at
middle
is
probably
worth
pointing
out.
C
First,
it's
a
very
common
one,
so
pretty
much
all
of
the
test
benches
we'll
see
later
use
a
parameter
type
along
these
lines
called
PBT
with
three
Fields
PV
and
T,
where
one's
a
corner,
one
is
a
numeric
thing,
we'll
look
at
later
and
the
license
temperature.
So
here
we've
got
a
test
bench
at
bottom
for
vco,
where
it's
got
its
set
of
parameters
and
then
the
sort
of
simulation
setup
has
its
own.
C
Using
these
generators
looks
a
lot
like
using
parametric,
bear
log
modules,
the
general
gist.
Is
we
sort
of
call
them
twice?
The
last
two
lines
on
the
slide
are
really
what
I'm
pointing
at
there,
which
is.
Should
we
call
them
the
first
time
to
give
the
parameters,
call
them
the
second
time
to
give
connections.
C
C
So
I
call
this
an
analog
htl,
there's
not
much
in
all
honesty
that
has
been
specifically
analog
about
it
that
I've
shown
yet,
but
one
of
the
things
that
really
make
it
so
is
Distortion
of
what
components
does
the
system
bring
to
the
party?
What
are
their
primitive
elements?
So
what
do
I
mean
by
that
by
analogy
to
a
procedure,
programming
language?
If
this
is
C,
let's
say:
there's
you
can
the
programmer
can
Define
structured
types?
C
This
programming
is,
if
this
program
is
say,
running
a
sports
League,
there
might
be
structures
for
a
league
and
team
and
player
and
then
somewhere
at
bottom,
it
gets
to
things
like
string
and
float
un64
that
the
programmer's
not
bringing
to
the
party
right.
The
system
is
doing
that.
These
are
the
Primitive
elements
and
what
are
those?
What
is
the
set
of
those
is
kind
of
an
important
definition,
old
facet
for
a
project
like
this
and
well.
C
There
is
basically
the
spice
Primitives,
so
basically,
the
things
more
or
less
the
things
that
are
built
into
space
are
what
are
also
built
into
hdl21.
So
in
this
example,
the
designer
can
make,
let's
say,
a
PLL
which
includes
a
charge
bump,
which
includes
an
op-amp
and
the
things
that
the
system
are
is
bringing
to.
The
party
are
things
like
nmos
and
resistor,
and
capacitor
they're,
in
fact,
very
highly
inspired
by
some
of
our
Berkeley
hosted,
like
original
spice
documentation,
lists
of
the
sort
of
built-in
components.
C
C
The
list
of
them,
if
we
many
of
these
QR
code,
links
by
the
way,
lead
to
the
hdl21
ghetto
repository,
the
list
of
them
is
on
there
comprehensively
and
excerpted
here
their
couple
of
other
ideas.
Amongst
these
primitive
elements,
one
is,
there
are
sort
of
Ideal
and
physical
flavors.
The
former
is
more
like
what
I
said
in
being
directly
implemented
by
a
simulator.
The
latter
is
more
a
Target
to
be
sort
of
expanded
to
a
Target
technology
and
we'll
see
some
examples
of
that
shortly.
C
So
if
you
want
to
get
out
of
page
still,
21
you're
going
to
produce
industry
standard
stuff,
that's
one
of
the
central
tasks,
so
net
listing
Works
through
that
picture,
I
showed
earlier
of
vlcir
as
a
sort
of
intermediate
interchange
produces
vlsir
protobuf
and
then
some
of
the
vlsir
paired
software
can
turn
that
into
your
favorite
netlist
formats.
Space
expect
various
spice,
flavors,
Specter
and
the
like
so
exporting
to.
C
C
There's
one
sort
of
special
field
here
which
is
called
TB.
That's
the
test
bench
module.
You
you've
seen
some
attempts
that,
let's
say
automating
generating
new
simulations
that
are
pretty
structured
and
rigid
and
painful
to
my
eye.
Ours,
I
I,
think
his
Works
quite
well,
which
is
that
anything
is
a
test.
Any
module
can
be
a
test
bench
if
it
meets
this.
One
sort
of
nested
criteria
left
here,
which
is
a
spice
test
bench,
is
a
module
that
has
exactly
one
port.
C
It's
exactly
with
one
and
we're
going
to
hook
it
up
to
ground,
so
you
can
think
of
the
sort
of
netlist
layer
as
having
a
single
node
zero.
We
hook
it
up
to
a
circuit
that
gets
provided
here
called
TB.
This
is
the
one
thing
it
takes
to
be
a
spice
test
bench
in
the
system,
a
more
realistic
one
which
has
VSS
as
the
port
and
then
some
signals,
a
duty
module
and
a
voltage
source.
That's
another
one
of
our
Primitives
by
the
way
hooked
up
between
them.
C
E
C
So
the
clearly
they
don't
probably
even
know
about
this
project.
Okay
I,
certainly
don't
provide
this
stuff.
The
good
news
is,
there's
not
all
that
much
to
provide.
So
generally.
What
these
pdk
packages
include
is
a
group
of
when
you
think
of
as
module
headers
the
they're
called
external
modules
in
the
system.
Other
kind
of
comparable
projects
like
chisel,
also
here
at
Berkeley,
call
them
black
boxes.
C
C
So,
let's
start
at
part.
One
part
two
is
there's
one
pdk
compile
method
for
each
of
these
packages
and
the
general
gist
of
that
is
actually
the
next
slide,
which
is
take
these
generic
primitive
elements
that
we
looked
at
earlier.
So
hsi1
provides
all
of
these
sort
of
process,
agnostic,
transistor,
resistor
and
the
like,
and
each
technology
has
a
compile
function
that
essentially
Maps
them
into
their
own
types,
their
own
devices,
so
the
circuit
I
showed
on
the
prior
slide
is
called
the
sky
in
it
creates
insert
it
directly.
C
C
So
that's
one
of
the
important
elements
of
kind
of
process,
Independence,
there's
I,
say
this
is
kind
of
for
the
analog
tribe,
some
of
what
I
mean
by
that
is
just
in
points
of
emphasis
more
than
in
kind
of
Technology
right
and
one
sense
in
which
I
mean
that
is.
There
are
built-in
Notions
of
things
like
just
the
fact
that
there's
going
to
be
stuff
outside
that's
not
python
code,
that's
necessary
for
interacting
with
these
Technologies.
C
C
It
might
be,
where
is
some
library
of
cells
that
comprise
a
standard
cell
library
or
some
other
cell
library,
and
the
other
helpful
paired
facet
is
by
convention
each
kind
of
file
system
or
site
or
server
defines
a
module.
A
short
python
file,
like
you
mentioned
name,
site
pdks.pi.
This
sort
of
sets
all
these
up
right,
so
create
these
install
things
for
any
pdks
that
it
wants
to
run.
Any
helpful
thing
about
this
is
that
it
does.
It
makes
this
separation
such
that
we
can
distribute
code.
C
Login
them
separate
from
the
details
of
whoever's
process
is
going
to
run
them
right.
So
you
can
discount
this
as
a
headache
but
for
I
think
most
of
these
projects,
kind
of
Step
One,
is
down
below
the
source
code
and
start
modifying
it
to
reflect
your
file
system
stuff,
your
sort
of
computers
and
stuff
and
I
think
that
is
in
the
way
of
a
lot
of
very
helpful
things
like
being
able
to
use
the
central
package
managers
to
distribute
these
things.
C
C
C
It's
not
necessarily
obvious
that
it's
not
a
great
idea
to
use
floating
Point
numbers
for
things
like
the
physical
dimensions
of
IC
elements,
but
it
isn't,
and
particularly
because
the
voting
Point
numbers
are
subject
to
floating
Point
error
and
the
elements
often
have
allowed
and
disallowed
values.
I.
Think
of,
like
the
length
of
a
moss.
Transistor
right
might
have
values
that
are
10.
C
Nanometers
allowed
16
nanometers
allowed
20
nanometers
Allowed,
no
other
numbers
in
between
are
and
those
nowhere
is
it
written
that
those
need
to
follow
on
by
Tripoli
floating
Point
values,
so
what
we
provide
and
The
Primitives
particularly
rely
on
this?
Are
these
prefix
numbers,
the
general
gist?
Is
there
is
a
decimal
value,
numeric
part
and
an
SI
prefix,
so
micro
manual,
femto
Etc
expose
those
as
their
sort
of
normal
single
character
names
and
then
what
I
think
makes
it
look
very
intuitive
to
use.
Is
this
multiplication
operator
one
times?
C
Mu
means
one
micro
and
20
times.
N
means
20
Nano,
so
that's
essential.
That's
especially
useful
for
the
Primitive
elements
sort
of
at
the
bottom
of
the
hierarchy.
Those
are
a
lot
of
tools
up
hierarchy
right,
so
we've
looked
at
that
schematic
earlier,
which
had
tons
of
ports
that
were
like
sub
block.
One
underscore
Sub
sub
block
2
underscore
Sub
sub
block
three
underscore
reset
all
right,
and
that
kind
of
stuff
happens
a
lot.
You
have
signals
that
travel
together
system
bear
log
introduced.
It
has
an
idea
for
this.
C
What
she
calls
interfaces.
Another
popular
project
here
at
Berkeley
chisel
calls.
This
idea
bundle
with
a
all
share.
Are
their
structured
connections
and
you'll
often
hear
from
analog
designers
like
I?
Don't
do
that
and
they're
wrong?
They
do
it
all
the
time.
Very
very
common
example
is
a
differential
pair.
So
this
one
is
popular
and
common
enough.
That
it's
sort
of
built
in
pnn
or
the
two
legs
that
didn't
pair
and
you
can
Nest
them
right.
C
So
quadrature
is
a
thing
that
gets
instantiated
all
over
the
fire,
we'll
look
at,
which
is
an
in-phase
differential
pair
and
a
quadrature
phase
differential
pair,
and
you
can
create
that
bundle
of
signals
very
similarly
to
creating
a
system
modules,
just
call
them
and
then
can
connect
to
the
subpart.
So
here
we
have
a
diff
amp
on
I
and
a
diff
amp
on
Q
reaching
into
the
DOT
index.q.
C
There's
differential
is
kind
of
a
special
enough
case,
well
that
well
bundles
can
be
defined
arbitrarily
in
a
user-defined
ones.
All
over
sort
of
large-scale
circuits
diff
is
common
enough
to
be
built
in
and
has
a
paired
facility
called
pair,
which
is
two
identical
instances
right.
So
this
is
another
thing
that
comes
up
all
the
time.
The
point
of
this
slide
is
really
the
last
two
lines.
A
pair
of
some
module
or
other
instantiable
thing
makes
two
of
them
here.
C
We're
making
an
nmos
resistive
loaded
amp,
which
the
nmos
connection
goes
to
You'll
note.
The
input
and
output
are
both
these
differential,
bundles
and
the
load
is
probably
the
best
way
to
point
out
that
one
side
of
that
diff
pair
goes
to
the
differential
output.
One
pair
goes
to
the
scalar
signal
bdd,
the
general
just
is:
if
these
things
get
hooked
up
to
a
diff
pair
hook
up
pnn
to
the
two
legs
of
the
pair
being
hooked
up
to
a
scalar
signal,
hook
them
up
comparable.
C
That
works
for
more
than
primitive
elements,
so
a
very
popular
circuit,
you'll,
see
including
later
in
this
talk,
is
sort
of
pseudo-differential
oscillator
stage,
with
forward
inverters
and
cross-coupled
inverters,
which
have
a
certain
ratio
in
strength.
Creating
those
as
a
pair
is.
This
is
a
literal
module,
we'll
use
and
see
later
lots
of
other
stuff,
so
lots
of
the
other
niceties
that
you're
kind
of
used
to
they're
built
up,
including
instant
arrays
of
instances.
C
So
this
is
sort
of
syntax
built
into
verilog
or
the
sort
of
angle
bracket
thing
built
into
virtuoso,
I.
Think
an
even
more
helpful
realization.
Here
and
again,
the
point
of
this
slide
is
really
the
last
line.
Is
that
an
instance
of
a
module
times
an
integer
is
a
great
way
to
create
these
things
right,
so
the
last
line
is
making
three
instances
in
an
array
of
this
child
module
at
top
and
kind
of
related
to
that
is
placing
and
concatenating
signals.
C
So
all
the
signals
are
sort
of
buses,
they
are
all
Vector
with,
and
there
are
facilities
for
concatenating
them
together
into
bigger
ones
and
then
slicing
them.
Apart
with
the
built-in
python
syntax,
the
square
bracket
operators,
the
sort
of
the
usual
in
language
idiom
for
doing
so,
this
resistor
ladder,
which
gets
used
as
part
of
a
DAC
project,
defines
sort
of
top
and
bottom
ports
a
bunch
of
TAPS
in
between
and
then
concatenates
them
into.
C
This
R
units
is
for
virtuoso
users
very
much
like
the
sort
of
wrap
around
syntax
with
the
comma
separated
concatenation
and
then
splitting
out
one
of
those
to
tie
to
a
single
capacitor
at
the
end.
Okay.
So
this
is
a
good
rundown
of
what's
in
htl,
21
and
I
sort
of
motivated
this
with
these
very
bad
schematics.
And
hopefully
it's
come
across
that
I.
Think
in
general
semests
are
bad
and
they
should
probably
be
code
and
you
might
be
able
to
guess.
C
Like
I
said
earlier,
I
I
can't
on
some
level
describe
what
this
is,
but
on
another
level,
I
understand
this
picture
so
much
better
than
the
code
version
thereof
right.
So
this
is
a
great
example.
Another
great
example
of
kind
of
wacky
analog
schematics,
and
these
are
all
actually
examples
from
The
Forum
that
brought
this
to
mind,
which
is
here
at
Berkeley.
C
We
give
all
of
the
grad
students
in
circuits
an
exam
where
we
give
them
kind
of
wacky
circuits
like
this
and
have
them
explain
how
do
they
work
or
make
another
one
similar
to
it,
and
it
was
really
while
helping
the
students
this
year
prepare
for
that
that
I
realized.
You
know
at
this
kind
of
primitive
level.
C
It
really
is
much
more
descriptive.
It
really
does
land
a
lot
better,
including
with
me
to
describe
this
circuit
this
way.
So
we
saw
all
of
the
good
things
about
the
HDL
code
earlier
and
I'm,
going
to
tweak
that
prior
statement
to
say
most
schematics
and
I
think
most
by
quantity
fall
in
the
earlier
ugly
category
are
bad
and
most
should
be
code,
but
there
are
some
good
ones,
and
so
how
do
we?
How
do
we
get
the
good
without
the
bad?
C
C
Second
be
shareable,
don't
require
I
actually
had
to
re-stand
up
virtuoso
to
draw
those
ugly
schematics
I
showed
you
earlier.
It
took
me
like
all
morning
to
get
through
all
of
the
various
layers
of
software
required
to
connect
in,
and
you
really.
We
really
shouldn't
need
that
to
convey
something
like
that
picture.
I
showed
a
few
moments
ago
and
make
the
good
ones
easy
and
bad
ones
hard
right,
so
I
think
to
Central
realization
is
the
schematics
are
two
things:
two
Central
things
one's
there.
C
C
Can
we
get
something
in
sort
of
easily
renderable
easily
visible
pictorial
form
it
also
pairs
with
that
kind
of
structure
and
there's
a
format
that
is
I
think
particularly
well
suited
to
that
which
is
SVG.
Svg
is
scalable,
vector,
graphics
is
one
of
the
sort
of
web
systems
Central
formats
along
with
HTML
JavaScript
webassembly.
C
This
is
an
XML
format,
so
it's
text,
looking
like
the
stuff
at
bottom,
left
that
your
browser
knows
how
to
turn
into
pixels
on
the
screen
right.
It
knows
to
turn
this
rect
into
a
rectangle
at
a
particular
location
of
your
screen
and
the
like.
It's
also
structured.
So
it's
XML
data.
It
has
semi-custom
metadata
and
structure,
which
is
what
you
can
use
to
embed
things
like,
say,
a
structural
circuit.
C
C
It
does
not
rely
on
linking
to
some
external
database,
at
least
to
show
you
the
schematic
picture,
so
so
sites
like
GitHub
can
render
them
any
web
browser
standing
on
its
own
can
render
them
lots
of
other
general
purpose.
Pieces
of
software
can
render
them.
If
I
email
you
one
of
them,
you
will
be
able
to
open
it
on
its
own
as
that
file
and
look
at
it,
which
I
think
is
a
really
important
element.
I
think
it's
another
counter-intuitive
facet
that
most
of
this
stuff
is
read
mostly.
C
So,
even
when
writing
you
are
mostly
reading.
So
what
do
these
look
like?
This
is
a
real
life
example.
This
is,
in
fact
The
Upfront
example
of
this
inverter.
This
is
an
SVG
file
that
also
contains
the
structure
of
that
inverter.
If
I
add
the
emoji
for
the
mind,
blown
emoji
from
open
Emoji,
it
remains
a
valid
schematic.
This
still
runs
and
simulates
and
does
all
of
the
same
stuff.
So
how
does
it
run
and
simulate
and
do
all
the
same
stuff
is?
C
The
easiest
way
I
can
imagine,
is
they
import
directly
as
though
they
were
python
modules,
so
the
language
has
a
nice
facet,
that
is
its
import
keyword
or
it's
include
external
stuff.
Keyword
is
in
a
sensible
variable,
and
the
system
includes
a
relatively
simple
mechanism
for
given
a
file
named
inverter.sch.svg
import
inverter
gives
you
that
schematic
as
a
generator,
so
there's
a
demo
repository
linked
at
bottom.
It
is
an
only
slightly
more
complicated
and
useful
example
than
this,
where
we
import
from
a
schematic
and
start
instantiating
an
HDL
code.
C
What
is
the
sort
of
thing
that
gets
imported?
Look
like
is
a
relatively
straightforward,
I
think
mapping
into
the
stuff
we
saw
earlier
right,
so
each
instance
of
A
Primitive
element
I'm
just
call
it
an
element
turns
into
an
instance
in
the
generated
module.
The
ports
turn
into
hdl21
ports,
the
wires
turn
into
signals,
and
you
get
something
very
much
like
what
we
were
describing
earlier,
so
sort
of
inverting
yeah.
F
C
C
There
are
a
couple
of
ways
you
can
run
that
we'll
see
sure
ladies
editor
platforms
and
then
there's
a
very
short,
a
very
concise
mechanism
for
turning
this
into
executable
python
code.
So
the
ways
to
interact
graphically
with
these
schematic
pictures
first
there's
a
dedicated
application,
so
this
uses
all
of
the
web
stuff,
which
has
made
it
very
very
fast
to
bring
up
right.
C
It's
really
just
been
me
working
on
this
very
recently
and
getting
to
the
phase
it's
at
in
that
short
amount
of
time
has
been
a
real
asset
of
having
that
web
stack.
Now,
for
a
lot
of
Eda
stuff,
you'd
say:
well,
that's
definitely
going
to
be
way
too
slow,
but
this
brings
in
another
important
trait
about
schematics,
which
is
they
really
can't
get
that
big,
or
at
least
they
can't
get
that
big
and
be
useful,
so
you're
never
going
to
have
a
million
elements
schematic
at
least
useful
one.
C
So
that
is
the
other
primary
mechanism,
which
is
this
vs
code
extension.
So
that's
become
sort
of
the
most
popular
I.E
over
the
last
few
years
and
is
relatively
straightforward
to
map
something
like
that:
GUI
application
into
an
extension
that
runs
when
you
click
on
a.netch.svg
file.
You
get
the
GUI
to
manipulate
this
bipolar
circuit.
C
You
also
get
some
nice
things
that
kind
of
like
I,
don't
know.
There's
some
level
of
kind
of
built-in
abuse
to
working
in
this
field.
I
think
that
you
just
don't
realize
you
can
get
stuff
that
was
invented
after
like
1990
like,
for
example,
when
your
computer
goes
into
dark
mode,
your
schematics
can
go
with
it
and
right
back
into
light
mode
along
with
it,
and
that's
another
part
of
the
premise
of
bringing
this
into
this
kind
of
more
modern
era
set
of
stuff.
C
So
I
described
it.
These
are
kind
of
graphical
code
and
there's
an
important
element.
There
are
a
couple
of
important
facets
of
how
that
works.
First
is
kind
of
how
does
it
know
what
to
refer
to?
How
does
it
know
what
these
transistors
and
resistors
and
the
like
are,
and
in
general
just
is
that
there
is
a
sort
of
code
section
to
each
of
these
schematics.
We
call
it
the
code
Prelude,
because
the
idea
is
that
it
sort
of
runs
before
the
pictorial
part.
C
F
C
So
if
you
think
of
this
code
running
first,
it
defines
this
p-bias
thing,
which
is
a
sized
transistor
sort
of
parameters
applied.
Transistor
p
cascode
is
a
different
size,
it's
much
smaller
common
tactic
and
our
bias
is
similarly
sized
and
then
the
identifiers
on
the
schematic
elements
really
refer
to
those
identifiers
right.
So
this
is
sort
of
a
way
to
say.
While
this
thing
changes
both
of
these
two
transistors
change
with
it,
foreign.
C
C
So
this
is
different
from
other
systems
I'm
familiar
with
in
that
the
picture
part
the
elements,
the
circuit
elements,
this
picture
representing
an
nmos
transistor
or
that
representing
npn
or
PNP,
really
just
bring
two
things
to
the
definition.
One
is
the
picture
itself.
What
it
looks
like
two
is
the
port
list,
and
this
we
call
of
string
here.
C
This
thing
that
says:
nmos
parentheses
is
really
what
dictates
what
it's
going
to
end
up
being
in
a
net
list
in
an
HDL
generator
and
the
like,
so
that
can
be
any
of
the
stuff
we
looked
at
earlier
right.
It
can
be
from
a
specific
technology.
It
can
be
the
built-in
generic
Primitives
they
can
get
compiled
after
the
fact
to
a
specific
technology
as
long
as
they
match
that
port
list
they
work.
C
C
So
if
you
want
it
to
be
voltage
controlled
type
in
vccs
and
you
want
to
be
controlled
type
in
cccs,
and
that's
really
how
this
kind
of
linkage
works
this
this
no
attached
sort
of
entombed
in
database
and
really
sort
of
links
through
these
code
code
identifiers,
where
do
these
live,
is
essentially
at
the
bottom
of
the
hierarchy.
Instantiating
things
that
are
similar
not
identical
to,
but
analogous
to
the
hdl21
Primitive
Library,
transistors,
resistors,
passives
inductor
and
the
like.
Our
examples.
C
C
B
C
C
D
C
We've
seen
projects
that
have
to
write
whole
piles
of
software
in
order
to
infer-
and
here
we've
got
a
real
opportunity
to
just
have
the
designers
tell
it
right.
We
have
this
sort
of
open-ended
space
to
say
both
in
sort
of
additional
structure
about
what's
a
pair
or
what's
an
array
or
whatever.
We
also
have
sort
of
open-ended
places
to
fix
these
things
to
the
HDL
objects
directly.
So
if
that's
I
think
that's
potentially
helpful
as
a
pairing
with
some
of
the.
B
We
do
we
have
a
lot
of
you
know,
description
on
in
vailog,
right
and
I.
Think
in
in
your
framework.
It
might
be
useful
to
try
and
see
how
we
can
reuse
that
we
don't
go
too
much
in
details
right
like
it's,
not
a
transistor
level,
it's
more
of
an
auxiliary
cell,
which
is
much
much
it's
more
like
a
standard
cell
level.
So
I
think
it's
great
to
try
this
and
and
there's
also
another
opportunity
here
to
discuss
about
integrating
this
within
opendb
I.
B
C
It
might
be
worth
rewinding
to
an
earlier
section
that
was
all
about
the
bsir
design
database
yep,
but
certainly
happy
to
chat
about
all
the
above
sure.
Okay,
very
short,
section
layout
I,
said
earlier.
We
would
run
out
of
time.
We
were
in
a
time
even
faster
than
I
expected,
really
layout's
going
to
be
maybe
next
time,
I
have
lots
of
thoughts
about
programming
layout.
What
I'll
do
for
now
is
just
flash.
C
C
This
is
you're
not
familiar
with
it.
You
think
of
it
as
kind
of
modern
c
replacement
that
can
be
embedded
very
directly
in
either
your
C
code
or
any
of
your
scripting
language
code
and
runs
at
Native
speed.
So
we
can
talk
about
layout
in
another
session.
What
I'll
briefly
go
through
instead
is
work
on
this
USB
file.
The
motivation
and
goals
for
doing
this
were
twofolds.
C
One
is
has
kind
of
a
more
elaborate
than
the
things
I
showed
earlier
demo
case
for
all
the
software,
but
also
making
something
useful
for
this
community
right.
We've
I
think
it's
been
really
beneficial
that
we've
had
all
of
this
attention,
and
you
know
energy
in
Sky
130
and
we
thought
well
what
is
a
practical
project
in
that
space
and
another
30
nanometer
that
technology
came
out
in
some
something
like
the
20
years
ago.
Range
2002.
C
We've
got
a
group
here
that
has
a
lot
of
Serial
link,
expertise
and
backgrounds.
That's
where
a
lot
of
my
work
has
been,
and
we've
also
seen
a
need
for
stuff
in
this
open
Hardware
space.
To
be
able
to
talk
to
you
know,
host
PC
like
having
one
of
these
USB
links
would
prove
very
helpful
to
a
lot
of
the
projects.
I've
seen
come
through
that
pipeline,
so
the
generation
that
came
out
around
that
time
is
what's
called
version
2.0.
C
It
runs
just
under
half
a
gigabit
at
480
megabit
and
that's
what
we've
been
making.
So,
what
that
looks
like
as
far
as
kind
of
block
diagram
getting
back
to
processor
or
processor-based
system
is,
if
you
think,
of
starting
at
kind
of
compute
at
left.
There
will
generally
be
some
some
bus
actually
being
very
popular
tile
link
here,
talking
to
a
block
generally
referred
to
as
a
USB
controller,
and
hopefully
this
generation
of
that
interface
also
defines
a
standard
controller
to
Phi
interface.
C
C
So
there
is
a
helpful
fact
about
this,
which
is
this
is
deterministic
and
recoverable.
Equalization
is
generally
the
idea
of
we're
going
to
invert
that
frequency,
dependent
loss
of
the
channel
and
sort
of
apply
the
inverse
transfer
function
at
the
receiver
or
at
the
transmitter
or
some
combination
thereof.
C
C
So
many
don't
many.
It
was
called
embedded
clock
where
there's
no
explicit
clock
sent
from
transmitter
to
receiver.
The
receiver
is
to
recover
essentially
a
surrogate
transmitter
clock
from
the
data
transitions.
We
refer
to
that
General
problem
as
clock
and
data
recovery.
You
know
each
have
their
own
sort
of
frequency
reference,
Crystal
or
similar,
but
turning
getting
this
receiver
to
take
incoming
data
stream
and
turn
it
into
good
sampling
instances
to
essentially
create
a.
C
This
has
worked
in
a
ton
of
places,
it's
been
very
effective
scheme.
One
problem
applying
is
to
USB
and
we
honestly
started
off
making
something
very
much
like
this
is
this
Loop
is
there
is
a
feedback
loop
in
producing
net
recovery
clock
and
it
does
take
some
time
to
settle,
there's
generally
some
sort
of
sort
of
Link
or
protocol
level
setup
to
say
you
get
this
many
bits
where
we
ensure
transitions.
C
In
contrast,
it
has
a
very
easy
version
of
the
equalization
problem,
and
so
our
high
speed
Phi
looks
more
like
this,
which
is
there's
no
dedicated
EQ,
but
we
do
have
some
I
think
relative
Innovation
on
the
clock
recovery
front,
which
is
it
uses
injection
locking
so
primarily
for
the
CDR
primarily
to
do
this
almost
immediate
term
syncing
to
incoming
data
edges.
We
then
apply
that
same
injection,
locking
to
the
TX
PLL.
C
So
there's
one
Central
goal
here
is
there's
a
very
small
fraction
of
what
like
an
industrial
team,
would
have
to
produce
such
a
piece
of
Ip.
So
minimizing
the
amount
of
stuff
is
a
really
Central
goal
and
actually
getting
that
sort
of
phase
interpolator
system
to
the
point
where
it
can
do
these,
what
we
generally
call
Burst,
Mode,
CDR
things
where
it
can
wake
up
in
just
a
few
UI
requires
quite
a
bit
more
Hardware.
C
F
C
Idea
is
there's
some
spinning,
oscillator
and
think
of
it
having
some
little
reset
switch
into
it,
that
the
sort
of
input
clock
tells
it
okay
go
back
to
phase
zero
right
now,
there's
that
is
all
descriptive
of
kind
of
the
480
megabit
stuff.
Usb.
Has
this
other
unfortunate
lineage
that
it
has
to
kind
of
walk
up
its
old
Generations,
many
of
which
are
higher
voltage?
C
C
It
is
all
in
Python
Landry,
which
is
very
helpful
in
that
it's
the
same
place
that
a
lot
of
similarly
situated
folks
want
to
do
things
like
data
analysis
and
figuring
out.
How
should
we
resize
the
circuit
and
what
is
going
to
be
enough
coverage
over
some
frequency
range,
so
Test
example
test
bench
at
left,
relatively
simple
one
for
one
of
the
preamps
that
gets
simulated
results,
get
pulled
back
in
or
get
spat
out
to
something
like
at
bottom
right.
C
So
we'll
we'll
have
more
to
share
on
sort
of
parametrics
and
performance
and
the
like
of
defy
as
that
gets
closer,
and
it's
in
progress
like
I,
said
and
I
hope
that
it's
gonna
be
I,
think
it
can
be
helpful.
I
would
point
to
really
this
whole.
All
of
the
things
I've
talked
about
this
talk
are
really
welcome
for
contribution.
C
C
The
controller
is
outside
the
scope
to
date,
and
if
there
are
contributors
or
if
there
are
folks
who
are
interested,
it
could
be
a
great
pairing
because,
like
I
said,
we've
got
some
folks
who
have
this
kind
of
knowledge
on
the
right.
That
I,
don't
think,
is
very
easy
to
find
in
this
community,
and
so
you
know
work
kind
of
further
to
the
left
of
this
picture
or
pairing
of
other
work
of
related
work.
Further
just
left
for
this
picture
go
a
long
way.
C
G
Great
thanks
so
I
was
just
thinking
about
the
backward
compatibility
of
HDL
to
one
from
the
spice
nutless
to
the
SVG
file,
because
that
that
is
actually
a
problem
which
has
been
facing
a
lot
with
you
know.
X
game
doesn't
support
it
and
there
is
this
python
Library
called
skim
draw
which
actually
helps
you
to
describe
the
circuit
using
all
the
stuffs
kind
of
similar
to
what
htl21
does,
but
it
only
expose
the
SVG
file.
It
doesn't
run
and
simulate
us.
G
C
So
I
think
there's
a
couple
of
categories
there
right.
So
one
is:
can
you
sort
of
parse
and
input
existing
net
lists
and
we
have
a
bunch
of
parsing
and
actually
another
Library
I
didn't
show
here
and
we
have
all
the
stuff
I
showed,
and
there
is
a
little
bit
of
linkage
in
between
them.
That
would
be
need
to
be
developed.
So
conceptually
it's
very
it's
not
very
far
off,
but
no,
it's
not
a
use
case
that
we
actively
do
well.
C
We
do
much
more
often
is
you
have
an
external
net
list
and
you
provide
one
of
these
module
headers.
One
of
these
external
modules,
which
sort
of
declares
the
I
o
to
the
modules
and
instantiate
that
so
part
two
is
the
interaction
with
schematics
and
I
am
familiar
with
the
skim
schematic
draw
Library.
That
is
a
sort
of
procedural
program,
for
that
says,
like
you
know,
draw
a
line
from
coordinate,
100,
comma
120
to
200
240
and
the
like.
C
The
way
you
create
them,
I
should
say,
and
the
way
that
you
create
HDL
code
is
by
writing
code
and
they
do
have
these
two
different
interaction
mechanisms
on
purpose,
because
I
think
those
are
the
sort
of
actually
the
intuitive
mechanisms
for
interacting
with
those
two
sort
of
modes
now,
could
you
infer
schematics
like?
Could
you
take
an
existing
netlist
and
you
know
try
to
infer
like
what's
a
good
picture
of
it
and
produce
it
in
this
SVG
format?
Absolutely
there
are
many
projects
that
do
so.
C
You
know
any
popular
or
many
popular
schematic
editors
have
them
built
in.
You
can
debate
their
quality,
but
they
at
least
try
I've,
seen
any
machine
learning
driven
one
in
a
recent
conference
publication
and
our
schema
and
format
is
open,
source
and
I
think
is
quite
straightforward
at
that
so
I
think
it's
a
pretty
natural
Target
for
such
things
would
also
be
you
know,
new
work
and
would
be
welcome.
G
C
Yeah
so
again,
there
won't
be
any
inference
of
circuit
pictures
from
from
HDL
code
and
as
far
as
running
in
Jupiter,
you
know
it's
still.
21
probably
you've
run
it
in
anywhere.
You
can
run
any
python
interpreter
right,
it's
you
can
if
install
and
import
it
in
Jupiter
or
anywhere
else,
there's
a
small
library
of
built-in
examples
that
are,
you
know,
kind
of
one
screen
length
programs
that
you
know
create
a
hopefully
both
simple
enough
and
useful
enough
circuit.
Many
of
them
were
actually
the
basis
of
the
slides
I
showed
here.
C
B
C
That's
ongoing
work
by
another
grad
student
researcher
here
to
produce
a
skywater
s3m
compiler,
more
kind
of
more
of
this
in
the
spirit
of
the
commercial
ones,
both
as
far
as
the
content
of
its
output
and
the
sort
of
parameter
space
that
goes
in
is
is
a
gentleman
Rahul.
Kumar
I
know
he's
gotten
lots
and
lots
of
interest
about
that.
As
that's
been
a
pretty
consistent
problem
for
many
participants
or
would-be
participants
in
the
open
source
shuttles,
that
is,
we
can
check
on
just
how
public
that
is.
C
B
B
E
Yeah
we
I
will
share
the
video
of
this.
That's
been
recorded
today
later
this
week
and
also
Dan
when
the
slides
are
available.
That
would
be
great
too,
and
just
as
another
point
is,
we
are
building
a
new
Chips
website
that
will
be
Hugo
based
and
hopefully
will
enable
easier
contribution
by
different
members
in
the
community
than
what
we
currently
have.
So
hopefully
that
will
help
aid
productivity
for
all.