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From YouTube: CHIPS Alliance - Analog Working Group - 2021-07-20
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A
A
It
sounds
like
very
promising
work
and
I
think
would
be
of
a
great
interest
to
the
analog
work
group.
So
with
that,
why
don't
you
go
ahead
and
take
it
away.
B
Okay,
thanks
rob.
Let
me
share
my
slides,
which,
for
some
reason,
don't
seem
to
be
showing
up
just
give
me
a
minute.
Please.
B
Okay,
so
thank
you
all
for
being
here.
This
is
a
presentation
of
the
align
project
and
we
have
several
people
from
a
line
who
are
on
this
call.
Today
the
main
presentation
is
going
to
be
made
by
me,
followed
by
steve
burns
and
sona
realities,
and
in
addition,
we
also
have
ramesh
harjani
from
the
university
of
minnesota
and
jiang
from
texas,
a
m
university
who
are
kind
of
faculty
members
who
are
leading
the
align
project
and
they
have
their
own
students
working
on
it.
B
So
like
several,
such
efforts
is
supported
in
part
by
the
darpa
idea
program
and
the
idea
here
is
again.
This
is
probably
a
very
simple
motivation
for
an
analog
work
group.
There's
analog
everywhere.
Interaction
with
the
world
real
world
is
all
analog.
There's
much
more
analog
content
on
chips
these
days
and
it's
really
been
the
last
frontier
in
design
automation.
It's
been
really
hard
to
automate
analog
in
part.
This
is
because
of
the
difficulty
of
the
problem
in
part.
B
A
couple
of
points
before
I
move
on.
I
don't
want
to
spend
a
lot
of
time,
belaboring
the
point
to
this
audience,
but
basically
one
of
the
things
is
that
analog
is
a
small
part
of
a
larger
digital
system,
but
in
terms
of
design,
difficulty
or
respins,
it's
actually
considerably
a
major
bottleneck.
So,
as
you
can
see
in
in
the
picture
on
the
left,
the
design
risk
is
shown
over
here.
B
It's
an
inverse
proportion
in
sunsets
to
the
area
occupied
by
this,
and
a
large
number
of
re-spin
issues
have
been
reported
to
be
ams
in
nature.
Now.
The
problem
that
we
are
tackling
here
is
automated
analog
layout.
So
typically,
your
designer
who's,
an
intellectual,
basically
designs
their
circuit
on
a
napkin
or
something
like
that.
This
is
a
beautiful
graphic
from
rob,
rutin
bar
and
then
somehow
this
has
to
be
taken
by
a
layout
engineer
to
something
like
this.
B
B
So
why
is
layout
important
if
you
think
about
the
overall
design
cycle?
There
is
like,
I
said,
the
circuit
designer
part
on
this
side
shown
in
red
and
then
the
layout
generator,
which
often
takes
days
to
weeks
and
then
once
you
get
the
layouts,
the
circuit
designer
basically
proceeds
on
assumptions,
of
course
estimations
of
parasitics.
Once
you
have
a
layout,
you
know
what
the
actual
parasitics
are.
So
this
might
mean
that
you
need
to
re-optimize
the
circuit
based
on
better
parasitics.
B
Then
you
perform
the
layout
again
and
then
you
go
through
a
set
of
multiple
cycles
and
the
overall
process
can
take
weeks.
So
if
we
could
somehow
shorten
this
to
perform
layout
in
an
automated
way
and
complete
it
within
minutes
or
hours,
this
would
really
be
great,
because
what
it
would
mean
is
that
I
could
estimate
my
parasitics
very
quickly.
I
could
shorten
the
optimization
cycle.
B
Now
people
have
been
looking
at
analog
layout
for
a
really
long
time.
In
fact,
professor
harjani,
my
colleague,
on
this
project
worked
on
this
for
his
phd
thesis
in
the
late
1980s,
and
his
work
was
a
pioneer
nearing
a
piece
of
work
because
it
got
a
best
paper
award
at
icy
cad.
I
believe
so
people
have
been
looking
at
this
for
a
long
time,
but
it's
really
had
a
lot
of
resistance
from
industry,
so
the
things
that
are
different
this
time
are
the
following.
B
The
first,
as
I
said
earlier,
is
the
fact
that
people
are
more
ready
for
it
and
one
of
the
reasons
they're
ready
for
it
is
because
you're
going
into
finfet
designs
these
days
now,
in
the
old
days,
designers
had
a
lot
of
degrees
of
freedom.
They
could
route
in
kind
of
clever
ways
etc,
but
in
with
finfet
design
rules,
there's
almost
freedom
from
choice,
in
the
sense
that
you
can
go
in
a
reserved
layer
at
the
in
the
bottom
layers.
B
For
example,
you
can't
really
do
kind
of
really
messy
things,
and
this
becomes
very
hard
for
a
human
designer,
but
it
reduces
the
search
space
for
a
design
tool.
B
The
other
thing
that
also
happens
is
that
the
constraints
can
could
potentially
be
expressed
more
clearly
now.
One
of
the
things
that
we
are
trying
to
do
in
a
line
is
to
be
a
sort
of
a
general
purpose,
layout
generator.
So
we
we're
not
targeting
just
data
converters
or
just
filters
or
just
operational
amplifiers
or
anything
of
that
sort,
we're
trying
to
address
a
wide
range
of
analog
circuits
and
we
think
of
them
in
terms
of
four
broad
classes.
One
is
low
frequency
analog.
B
You
can
think
of
these
as
otas,
for
example,
wire
line
or
high
speed
link
circuits,
and
these
are
things
like
dlls,
plls,
vcos,
clock,
data,
recovery,
etc.
There's
wireless,
which
is
rf
circuits,
so
all
components,
lnas,
mixers,
etc,
and
then
power
delivery
circuits
such
as
ntos
or
voltage
regulators
of
some
sort.
Now,
when
we
think
about
this,
there's
a
kind
of
a
taxonomy
of
constraints
that
we
put
together
for
this,
so,
for
example,
this
table
over
here
on
the
y-axis
shows
the
list
of
families
or
circuits
on
the
x-axis.
B
It
shows
a
set
of
kind
of
things
that
you
might
worry
about
and,
depending
on
the
class
of
circuits,
there
are
different
things,
different
things
that
are
start
that
are
really
important
and
things
that
are
in
light.
Colors
are
really
not
that
very
important
important,
so
really
one
of
the
things
to
go
from
kind
of
a
special
purpose,
layout
generator,
which
has
been
around
for
a
long
time
to
something
more
general
purpose,
is
to
capture
this
relationship
more
clearly.
B
The
third
thing
is
that
in
recent
years,
there's
been
a
lot
of
advance
in
machine
learning
and
we've
been
trying
to
exploit
that
in
several
of
the
steps
of
our
approach.
I
won't
be
able
to
talk
about
this
in
a
lot
of
detail
today,
but
these
are
some
of
the
things
that
are
helpful,
because
now
you
have
freedom
from
choice.
We
have
a
methodology
for
being
able
to
handle
a
wider
range
of
circuits
and
we
can
actually
exploit
machine
learning
which
wasn't
available
even
five
or
ten
years
ago,
let
alone
30
years
ago.
B
Our
approach
is
kind
of
really
heavily
driven
by
finfet
technology
nodes,
but
we
have
also
built
designs
in
both
node
65
nanometers,
for
example,
and
we
are
currently
targeting
sky
water
130
as
well,
so
even
in
the
finfet
world,
I
talked
about
freedom
for
joy,
from
choice,
but
things
are
still
pretty
hard,
because
just
kind
of
having
freedom
from
choice
quote
unquote
is
a
gross
oversimplification.
B
One
of
the
issues
is
that
this
is
data
from
an
intel,
a
paper
at
ic
cad.
If
you
look
at
the
gap
between
schematic
and
post
layout,
simulations
schematics
simulation
predicts
a
performance
of
something
like
this.
Mostly
our
simulation
predicts
a
performance,
that's
kind
of
much
further
away,
so
that
gap
is
kind
of
further.
So
this
means
that
the
design
cycle
actually
becomes
more
complicated
and
having
a
fast
layout
generator
is
extremely
helpful.
B
The
second
is
from
the
layout
standpoint
itself.
You
have
many
more
and
more
complex
design
rules,
so
this
is
an
example
of
a
hypothetical
design
rule
violation
which
is
typical
in
many
technologies
where,
for
instance,
it's
not
just
the
distance
between
vrs,
but
it's
the
vr
density
and
a
diagonal,
dense,
dense
distances
and
also
some
kinds
of
boolean
relationships
between
structures
that
need
to
be
incorporated.
B
A
third
factor
is
that
if
you
look
at
finfet
technologies,
they're
very
prone
to
self-heating,
because
you
have
these
long
and
high
fins,
so
you
cannot
call
it
finfet
trigate,
whatever
you
still
have
a
lot
of
thermal
concentration
over
here
and
that
needs
to
get
out
to
the
ambient
that
causes
self
heating.
It
causes
performance,
degradation,
reliability,
degradation,
etc.
So
these
constraints
have
to
be
taken
into
account
during
layout.
B
B
B
B
Now
as
part
of
this,
what
we
do
is
we
first
take
the
netlist
and
annotate
it.
So
we
recognize
structures
within
this.
So
from
this
list
we
don't
have
a
schematic
or
visual
representation,
but
we
recognize
that
there
are
some
circuit
blocks
in
here.
So
we
might
say
this
is
an
ota.
This
is
a
switched
capacitor
network.
We
might
say
that
there
are
some
symmetries
that
have
to
be
maintained.
This
is
automatically
done.
B
Then.
You
generate
electrical
constraints
which
say
that
if
you
want
to
meet
your
performance
text,
then
your
parasitic
should
be
no
larger
than
so
much
etc
and
at
this
point,
you're
now
ready
to
start
layout.
So
this
is
where
you
meet
up
with
the
pdk.
We
abstract
the
design
rules
generate
layout
for
the
lowest
level
blocks,
which
we
call
primitives,
and
these
are
things
like
differential
pairs
or
current
mirrors,
and
then
we
progressively
go
up
the
design
hierarchy
to
assemble
the
blocks
and
create
the
final
placement
float,
planning
and
routing.
B
So
this
is
in
a
nutshell.
What
the
overall
process
is.
Things
have
evolved
a
little
since
we
first
started
and
I'll
talk
about
that
later
and
we'll
also
have
a
demo
that
shows
that,
and
basically
the
quick
cheat
sheet
on
that
is
that
the
input
is
no
longer
just
over.
Here.
We
can
provide
inputs
at
multiple
points
over
here.
The
reason
we
can
do
this
is
because
we
built
a
line
to
be
very
modular,
so
you
can
bypass
a
module
if
you
so
desire-
and
this
turns
out
to
be
especially
useful
for
experienced
designers.
B
For
example,
we've
been
working
with
a
lot
of
intel
designers
and
they're
like
we
want
to
do
our
own
annotation.
We
don't
want
auto
annotation,
so
we
cater
to
designers,
ranging
from
absolute
amateurs
who
require
a
full
annotation
to
professionals
who
say
well,
we
want
more
control
and
we
provide
them
the
knobs
to
be
able
to
do
that.
A
A
Yeah
yeah,
I
I
know
from
my
experience
at
oracle
and
michelle
lotus
was
on
the
call
too,
who
I
worked
with
at
sunslash
oracle,
but
what
we
heard
consistently
from
the
custom
designer
analog
design
community.
There
was
the
need
for
very
such
very
such
things,
to
have
some
degree
of
control
when
necessary.
C
Thank
you
as
long
as
we're
paused
that
could
I
just
just
one
quick
comment:
this
is
dave,
so
I
in
the
spirit
of
open
source-
and
you
know
an
open
source
community
and
building
or
evolving
tools.
You
know,
maybe
one
thought
there
is,
if
you
guys,
provide
an
instead
of
just
skipping
the
annotation
step.
If
you
provide
an
annotation
and
then
allow
a
designer
to
like
confirm
annotations
or
say
no,
I
want
to
re-annotate
this
part,
but
you
got.
C
Yeah,
it's
just
you
know.
From
a
I
mean
from
an
ml
perspective
right,
the
usually
the
limiting
factor.
There
is
getting
good
labeled
data,
and
so
this
would
be
an
opportunity
to
add
labels,
essentially.
B
So
this
is
the
entire
align
team.
You
can
see
that
it's
a
big
project,
a
lot
of
people
working
on
it
and
they've
all
contributed.
So,
even
though
I'm
giving
the
presentation-
I'm
really
just
the
figurehead,
okay,
so
let's
become
a
little
more
concrete
and
let's
go
with
that
fish
capacitor
circuit
that
I
talked
about
a
little
while
ago
and
see
how
we
would
take
this
through
the
flow.
So
we
first
start,
although
I've
shown
the
schematic,
we
really
start
with
a
spice
netlist
over
here.
B
So
it's
really
a
set
of
lines
of
text
that
we
start
with
and
from
that
we
need
to
identify
these
structures,
so
we
first
go
through
a
annotations
step
which
would,
for
example,
identify
this
ota
and
within
this
ota
you
would
find
that
there's
something
like
this.
So
it
does.
The
netlist
doesn't
have
to
be
hierarchical
in
this
form
it
could
be
flat.
B
We
would
identify
this
ota,
then
within
the
ota
we
would
identify
sub
hierarchies,
so
you
can
see
that
there's
a
current
mirror,
a
differential
pair,
a
load
etc,
and
this
is
the
lowest
level.
At
this
point,
we
can
actually
do
kind
of
algorithmic
layout
generation
for
these
structures
that
we
call
primitives.
B
So
this
is
where
we
meet
up
with
the
design
rules.
We
abstract
the
design
rules
into
a
json
of
format
and
we
have
layout
a
layer,
specific
gridding,
so
every
layer
has
different
grading.
B
Then
you
take
these
and
you
put
them
together
into
a
layout
for
the
ota.
So
in
this
case,
for
example,
the
individual
structures
are
shown
over
here
and
they're
stacked
together
to
create
the
ota,
and
now
you
can
put
this
into
the
larger
structure.
So
the
ota
is
turned
by
90
degrees
and
placed
over
here
there's
a
line
of
symmetry
here,
similar
to
this
line
of
symmetry,
there's
a
bunch
of
capacitors,
which
are
these
huge
structures
and
some
switches
that
are
over
here
and
presto.
B
You
have
the
layout
for
the
switch
capacitor
filter,
so
the
overall
structure
is
something
like
this
and,
of
course,
there's
a
lot
of
sort
of.
There
are
a
lot
of
finer
details
involved
in
being
able
to
achieve
this,
so
I'll
go
over
these
step
by
step
fairly
quickly
right
now,
so
the
first
step,
like
I
said,
is
auto
annotation
and
constraint
generation.
B
B
So
there
are
some
details
over
here,
but
essentially
what
we
do
is
we
use
some
kind
of
a
machine
learning
approach,
so
we
have
a
netlist.
We
represent
the
transistors
and
nodes
in
the
netlist
using
a
graph,
and
then
we
take
this
through
a
graph
convolutional
network
to
say
well,
these
nodes
correspond
to
the
internal
nodes
of
an
ota
and
the
rest
of
them
are
outside
the
ot.
So
that
allows
us
to
cluster
this
and
create
the
hierarchy
for
the
ota.
B
We've
applied
this
to
a
few
other
circuits
and
the
confusion
matrix
basically
shows
that
we
are
able
to
identify
the
components
pretty
well.
However,
like
I
said
this
means
that
you
need
a
large
library,
you
need
to
have
a
training
set
for
every
type
of
structure
which
is
kind
of
painful.
So
if
you
look
at
some
structures
such
as
this,
for
instance
over
here,
you
clearly
have
a
repetition
over
here
in
of
the
comparator
array
and
the
r
array.
B
Similarly,
over
here,
you
have
binary
weighted
capacitors,
so
there's
repetition
over
here,
and
this
is
what
leads
you
to
understand
that
you're
going
to
be
doing
some
special
layout
structures.
So
the
other
thing
also
is
that
there
are
situations
where
you
might
have
approximate
matching.
So
in
this
case
you
have
a
common
gate.
B
So
by
using
these
approaches,
we
can
annotate
specific
structures
or
we
can
discover
hierarchies
and
we
can
discover
patterns
that
must
be
obeyed
in
the
layout.
So
this,
for
example,
shows
the
layout
of
an
r2r
dac,
and
you
can
see
that
we
identify
an
r
to
our
array
over
here.
The
switches
are
kept
separate
from
the
array.
B
Similarly,
this
is
a
10
tap
fire
equalizer,
and
you
can
see
that
there
are
10
structures
over
here
which
are
essentially
replicated.
But
the
interesting
thing
here
is
that
we
have
approximate
matching
here.
So
some
of
these
current
sources
are
five
bits.
Some
are
seven
bit,
but
we
can
identify
that
they
are
kind
of
roughly
similar
and
when
we
lay
them
out
the
seven
bit
structures
are
in
the
middle.
The
five
bit
structures
are
on
the
outside
and
this
is
a
layout
that's
automatically
generated
by
align.
B
So
that's
the
annotation
step.
The
next
step
is
generating
the
primitive
layouts
based
on
design
rules.
So
in
this
case
the
philosophy
is
actually
very
similar
to
the
classical
lambda-based
design
rules.
But
of
course
we
know
that
lambda-based
design
rules
don't
work
anymore,
so
the
modifications
that
have
been
made
are
aside
from
the
main
grid,
there's
a
subsidiary
grid,
which
is
like
an
endpoint
grid.
B
Over
here
we
introduce
the
notion
of
boolean
constraints
and
we
allow
layer,
specific
grading
so
for
a
bunch
of
commercial
pdks
as
well
as
kind
of
fictitious
or
mock
pdks,
that
we
and
other
people
have
created.
We've
been
able
to
abstract
these
into
a
relatively
simple
set
of
rules,
and
we
end
up
getting
the
layouts
that
are
pretty
competitive
with
human
layout.
B
Once
we
have
this
abstraction,
then
we
want
to
perform
cell
generation.
So
if
we
have
a
larger
circuit,
we
can
identify
structures
that
appear
often
in
this
case
we
are
looking
at
differential
pairs
that
appear
in
a
bunch
of
circuits,
so
we
would
want
to
have
a
primitive,
that's
called
a
differential
pair.
We
have
the
ability
to
parameterize
these
primitive
structures,
so
we
can,
for
example,
add
a
body
contact
or
not.
We
can
change
the
aspect
ratio.
B
If
it's
an
array
structure,
we
can
have
an
n
by
m
or
m
by
n
or
basically
any
other
permutation
of
the
array
structure.
We
can
use
parallel
wires
to
route
our
sensitive
connections,
because
these
can
degrade
the
transconductance,
for
example,
of
a
differential
pair
structure.
We
can
build
common
centroid,
interdigitated
structures.
We
can
change
the
number
of
fins
and
fingers
for
film
set
structures,
change
the
activate
change
the
gate
length.
B
All
of
these
are
important
for
various
circuits,
and
so
we
have
a
built-in,
primitive
library
that
has
these
basic
structures
over
here.
These
are
the
layouts
for
these
structures
and
we
allow
the
user
to
specify
new
primitives
as
needed
once
we
have
this.
The
next
step
is
performing
placement
for
planning
and
routing
and
then
basically
I'll
kind
of
go
through
this
very
quickly.
The
idea
here
is
that
we
perform
a
kind
of
a
high
level
placement
considering
global
placement,
considering
symmetry
alignment
matching,
etc.
B
We
perform
global
and
detailed
routing
cons,
considering
symmetry
minimum
length,
etc.
One
of
the
important
things
we
need
to
worry
about,
apart
from
symmetry
and
matching,
are
also
things
like
multi-path
routing.
So
this
is
basically
the
idea
that
you
need
multiple,
parallel
wires,
because
you
don't
want
to
be
resistance
constrained,
so
all
of
that
is
taken
into
account
over
here
we
perform
power
routing
as
well.
We
can
create
a
mesh,
we
can
try
to
make
sure
our
drop
constraints
are
met,
etc.
B
In
addition
to
this
router,
we
have
another
router
which
has
been
donated
by
intel,
which
is
basically
a
sat
based,
router
and
essentially
what
it
does
is.
It
takes
all
of
these
constraints
and
it
creates
boolean
representation
of
design
rules,
and
then
it
says
well,
if
I
have
a
structure
like
this,
with
cheap
routed
structures.
Now
I'm
very
constrained.
This
is
where
sat
excels.
Now
I
can
provide
a
very
constrained
space
to
sat
and
give
it
relatively
fewer
options.
B
B
We
also
have
some
kind
of
machine
learning
built
into
this
for
performance
estimation
and
again
this
is
just
a
very
quick
estimate
overview
because
I
want
to
hand
it
over
to
my
to
steve
and
persona
to
present
other
material.
But
basically
the
idea
here
is
that,
as
you
go
from
schematic
to
layout
generating
pretty
layouts
is
not
the
objective.
You
want
to
make
constraints.
So
when
you
go
from
schematic
to
layout,
you
want
to
make
sure
that
you
meet
your
performance
constraints.
So
basically
what
we
do
we
have
various
approaches.
B
One
of
them
is
to
use
a
graph
neural
network.
There
are
a
few
other
approaches
as
well
and
based
on
these,
we
check
at
every
step
whether
the
performance
is
good
enough
or
not.
So
when
we
generate
a
candidate
placement
for
this,
we
have
a
fast
estimator
based
on
machine
learning
that
checks
whether
the
performance
is
good
enough
or
not.
B
D
Okay,
can
you
hear
me
yeah
so
originally
in
the
project
we
started
off
with
in
a
very
decoupled
manner
when
we
built
up
the
the
software.
The
the
flow
as
we've
seen
in
pictures
before
is
divided
into
these
multiple
stages,
and
each
stage
was
developed
originally
more
or
less
at
one
site.
So
we
had
the
auto
annotation
stuff
done
at
minnesota,
and
the
layout
stuff
was
done
at
temu
and
and
primitive
stuff
was
done
at
intel
and
minnesota.
D
So
since
people
had
their
own
environments,
we
didn't
really
try
to
unify
them
very
early.
We
kept
this
decoupled
architecture
around
and
we
used
files
to
interface
between
the
different
stages
of
the
flow,
so
either
used
industry
standard
formats,
usually
simplified
versions
of
them
or
custom
json
schemas,
and
then
we
use
docker
as
a
way
to
bring
up
each
of
the
individual
build
environments
and
then
link
them
together
that
way.
D
So
that
was
a
good
way
to
start,
but
as
can
you
go
to
the
next
foil,
that
was
a
good
way
to
start,
but
as
the
project
matured,
we
we
sort
of
solidified
on
on
on
a
decent
common,
build
environment
and
we
converted
the
whole
project
over
to
to
a
python
centric
project
and
all
the
c
plus
plus
tools
where
we
put
pi
bind
11
wrappers
around
them
so
that
we
could
call
them
directly
from
from
within
python.
D
So
the
the
project
then
could
split
more
or
less
into
these
four
categories
of
a
compiler,
a
primitive
generator,
various
utilities
and
the
place
and
route
code,
and
there
are
two
different
place
and
route
engines,
this
hierarchical
place
and
route
tool,
and
then
this
sat
based
solver.
D
So
each
of
these
packages
is
now
a
python
package
they
can
be.
We
can
use
pip
install
to
install
the
entire
system
and
each
sub-package
is
more
or
less
independent
and
can
be
used
independently
for
different
things,
if
necessary,
so
that
next
flow,
please
touching
and
in
terms
of
you,
know
how
we
develop
things.
Now
we
use
github
to
for
source
control
and
team
communications.
We
have
lots
of
issues
lots
of
prs
around
we
communicate
in
pr's
about
about
what
needs
to
be
fixed.
D
D
We
have
a
continuous
integration
system.
Every
time
we
push
to
github
and
a
pull
request,
then
we
we
get
a
circle
ci
run
which
clones
the
repository.
Does
this
pip
install
and
runs
pi
tests
and
other
tests
checks
to
see
whether
they
pass
pushes
to
master
cause
more
extensive
tests
to
be
run?
So
these
pictures
over
on
the
on
the
right
show
that
those
are
the
circle,
ci
graphs,
so
for
a
a
push
on
a
pull
request.
D
We
just
do
a
simple
build
in
one
of
our
build
environments
and
then
we
we
do
some
integration,
testing
and
and
and
unit
testing.
When
we
push
the
master,
then
we
actually
run
it
through
a
bunch
of
different
build
environments.
D
D
D
I
think
sonner
had
many
foils
on
this
right.
Honor
yeah.
B
Yes,
so
why
don't
I
kind
of
hand
over
to
sauna
and
he'll
talk
about
these
alternative
entry
points
before
I
kind
of
jump
there
I'll
just
show
a
few
kind
of
sample
layouts
that
we've
generated
using
a
line.
This
is
sort
of
the
rogues
gallery,
and
this
continues.
We
handle
multiple
technologies
as
listed
over
here
and
again.
This
list
is
also
broadening
over
time,
so
I'll
pass
it
on
to
sonar
now.
E
Thanks,
I
will
keep
my
media
off
so
that
I
can
use
the
whole
screen
more
effectively,
so
I
will
start
with
few
slides
and
then
switch
to
a
vnc
to
show
the
tool
flow
in
action,
and
what
I'll
be
focusing
on
is
how
we
have
been
making
use
of
a
line
at
intel
exercising
on
power
management
circuits
in
the
22
ffl
technology.
E
E
However,
design
rules
are
making
this
harder
as
they
get
more
complex
due
to
multiple
patterning
and
density
rules,
so
his
reliability
is
making
it
harder
to
close
the
layout
due
to
this
either
self-heating
or
electron
migration,
and
on
the
top
right
figure.
Here
we
can
see
some
power
measurement
circuits
that
are
pretty
much
mandatory
in
any
modern
soc,
cpu,
gpu
or
fpga,
and
this
figure
is
showing
roughly
in
person
by
month
the
effort
involved
in
creating
the
layout
for
these
ips.
And
why
does
it
take
so
much
time
right?
E
The
the
bottom
right
figure
is
showing
a
cartoon
picture
where
analog
engineers
spend
some
time
on
deciding
on
the
topology
and
the
schematic,
sizing
and
then
hands
off
the
mask
designer.
The
first
objective
is
really
to
again
get
posted
out
parasitic
feedback.
So
that's
why
these
early
iterations
are
quick
and
dirty.
They
are
not
drc
clean
or
not.
Necessarily.
E
If
you
look
at
broadly
right,
the
previous
work
can
be
categorized
as
template
based
and
on
one,
and
then
also
optimization,
based
so
templates
based
approaches
can
generate
really
good
high
quality
layout.
This
has
been
shown
in
silicon,
however,
it
comes
with
a
high
coding
overhead.
On
the
other
hand,
the
optimization
based
techniques
are
a
lot
more
significantly
reduce
this
overhead
right
to
device
or
device
rate
generators
that
such
and
already
mentioned,
but
then
the
of
course
the
question
is
okay.
How
can
we
push
the
layout
quality?
E
So
what
we
are
pursuing
is
a
practical
and
modular
analog,
layout
generation
methodology
and
particularly
for
advanced
in
fifth
technologies,
and
one
way
we
are
achieving.
This
is
through
these
multiple
entry
points
to
accommodate
circuits
with
varying
performance
needs.
E
So
what
we
call
the
vanilla
align
flow
starts
with
this
netlist
right,
which
is
doesn't
have
any
annotation
no
constraints,
and
then
the
flow
is
fully
automated,
which
goes
through
each
of
these
stages
and
then
creates
a
layout,
and
this
seemed
to
work
for
what
we
would
call
non-critical
circuits
or
that
don't
require
special
attention
and
then
for
some
circuits.
E
This
may
require
assisting
the
automation,
especially
the
constraint
generation,
to
improve
the
layout
quality,
and
this
is
specified
in
a
domain
specific
language.
This
is
a
custom
language
that
we
have
in
creating
and
it
allows
users
to
provide
placement
routing
constraints
that
are
quite
simple
and
quite
a
few,
a
handful
of
these
constraints
to
improve
the
layout
quality.
E
Yet
there
are
still
few
very
demanding
circuits
that
require
more
control
by
the
engineer,
and
this
is
what
we
call
the
entry
point
three.
What
happens
here
is
now
in
python,
the
user
or
the
design
engineer
can
codify
the
placement
and
the
route
plan,
which
is
also
known
as
global
routes
and
then
still
utilize,
automated
detailed
routing,
where
this
is
still
a
big
hard
problem,
especially
with
advanced
intake
with
multiple
patterning,
and
if
we
take
this
to
the
extreme.
E
There
are
these
very
few
circuits
that
have
high
regularity
and
here
now
not
only
placement,
but
also
the
routing
becomes
quite
straightforward,
just
using
basically
multiple
for
loops,
and
there
are.
I
will
talk
about
some
examples
in
the
power
management
domain,
but
a
good
example
here
is
a
powertrain
which
is
really
nothing
but
a
very
big
transistor
array,
but
it
requires
special
consideration
to
reduce
power
density
and
also
minimize
ir
drop.
E
E
So
if
we
just
you
know,
take
a
quick
look
at
this
circuit,
you
can
realize
the
differential
pair
here
there's
a
cross-coupled
inverters
or
cross
couple
demos
and
pmos
pairs,
and
then
there
are
the
inverters
at
the
output.
So
these
are
some
functional
or
matching
sensitive
building
blocks
of
this
circuit
and
what
we
will
look
at
is
we
are
going
to
try
running
a
full,
automated
layout
and
then
generate
another
version
by
giving
some
constraints
to
the
flow.
E
E
If
you
want
to
also
create
a
power
grid,
then
we
can
create
a
setup
file
where
we
specify
the
name
of
the
power
and
the
ground
nets,
and
this
is
sufficient
to
get
started
with
using
your
line.
So
I'll
just
first
start
invoke
the
line
the
schematic
to
layout
and
then
see
the
best
solution
it
finds
out
of
the
box,
and
this
is
you
can
see
this
took
on
the
order
of
tens
of
seconds
okay,
I
thought
my
firefox
was
already
open,
maybe
not
okay,
sorry
for
this
glitch.
E
I
think
I
can
there
you
go
okay,
so
this
is
basically
the
layout
generated
right
now
and
we
also
saw
on
the
powerpoint
slide.
So
if
you
look
at
this
at
the
high
level,
what
happened
a
line
did
detect
the
again
this
matching
sensitive
pairs
and
then
interleave
them.
So
this
we
are
here
showing
the
seeing
the
differential
pair
and
then
the
cross
couple
devices
and
so
forth,
and
it
did
basically
generated
this
layout
by
trying
to
minimize
the
area
and
minimize
the
estimated
wire
length.
E
Other
interface,
which
allows
us
to
see
the
multiple
choices
or
multiple
options
and
then
pick
among
them.
So
here
what
I
did
is
we
asked
a
line.
Okay,
show
me
your
top
30
floor
plans,
basically,
and
here
on
the
left.
I
will
increase
this
a
little
bit.
You
can
see
an
area,
an
estimated
wire
length,
pareto
frontier-
and
there
are
you-
know
several
different
floor
plans.
That
line
did
explore.
So
this
was
the
comparator.
Zero
was
the
best
solution
that
we
saw,
but
then
let's
say
maybe,
for
example.
E
This
is
a
particular
solution
where
the
clocking
transistors
or
the
pre-chargers
are
all
consolidated,
which
would
reduce
the
coupling
so
for
to
the
trained
eye.
This
lets
you
to
choose
a
different
floor
plan
and
if
you
are
let's
say
happy
with
this,
we
can
continue
with
the
flow
and
then
get
the
layout.
E
Now,
if
we
have,
if
we
want
to,
we
have
basically
what
I
would
say,
strong
opinions
or
if
we
have
preferences
and
have
one
of
have
more
control,
then
we
can
do
the
entry
point
number
two,
where
we
can
specify
or
provide
some
constraints
to
the
flow.
So
here
I'm
just
gonna
copy
paste
this
and
then
run
it.
E
So
what
we
did
here
is
the
first
several
lines
these
group
blocks
are
saying:
these
are
the
transistors
that
you
want
to
be
interleaved
or
be
placed
in
proximity,
and
the
reason
we
define
here
is
later
on
the
line
number
seven
and
eight
we
are
defining
a
vertical
line
of
symmetry.
So
this
vertical
symmetric
placement
also
improves,
match
routing
and
reduces
the
offset,
and
the
nine
and
ten
specify
some
ordering
in
terms
of
top
to
bottom,
where
we
want
to
place
these
primitives.
E
There
is
a
on
line:
11,
there's
a
multi-connection
which
specifies
okay
for
the
tail
or
the
sore
common
source
of
the
diff
pair.
We
want
to
use
multiple
tracks
so
that
we
can
reduce
source
degeneration
and
then
the
last
one
is
an
aspect
ratio
which
tells
the
line.
Okay.
We
also
want
to
stay
within
this
bit
over
height
range.
E
E
So
I
will
go
back
to
some
results
that
we
get
using
this
flow.
So
here
this
slide
shows
again
flavors
of
comparator
layouts.
The
top
left
is
a
manual
handcrafted
layout.
This
is
created
by
a
expert
mass
design
engineer
and
then
you
can
see
different
flavors
of
this
that
were
generated
about
a
year
and
a
half
ago,
and
this
is
was
put
on
a
test
chip.
We
have
the
silhouette.
E
E
When
we
look
at
the
manual
layout
there's
a
lot
of
effort
put
into
the
initial
getting
base
layers
done
and
then
optimizing
the
interconnects
to
reduce
the
input
referred
offset
and
then
finally
design
root
closure.
So,
but
when
we
do
enter
point
one,
as
you
just
saw,
it
actually
takes
one
order
of
seconds
not
even
hours,
even
given
constraints
takes
on
the
order
of
minutes.
E
In
the
entry
point
three,
where
we
codify
the
placement
and
python
that
takes
a
little
bit
longer,
but
still
within
a
day,
it's
able
to
turn
around
the
layout
and
then
do
very
fast
iterations
on
it.
E
On
the
bottom
right,
we
see
performance
measured
from
60
silicon
samples,
so
the
left
figure
is
showing
the
input
referred,
offset
voltage
and
then
the
right
figure
is
showing
the
comparison
delay.
So
there
are
again
pros
and
cons.
So
if
we
compare
the
input
referred
offset,
we
are
all
of
the
generated.
Layouts
are
still
within
the
spec,
but
they
are.
There
is
still
some
work
to
do
to
get
to
the
level
of
manual
layout
and
also
the
from
the
delay
comparison
perspective.
E
So
we
can
see
here
he
you
see
that
ep3
is
very
close
to
manual,
because
it
is
actually
codifying
the
exact
same
placement
so
where
ep2
has
slightly
larger
delay.
That's
because
putting
these
on
a
vertical
line
of
symmetry
increases
the
interconnect
and
therefore
increases
the
delay
also
generated
analog
ldo
using
the
methodology
here
on
the
left.
You
can
see
the
manual
handcrafted
layout,
so
this
ld
obviously
consists
of
an
error.
E
Amplifier,
a
compensation
capacitor
and
the
big
analog
powertrain
and
the
right
layout
shows
how
generated
layout
through
a
line
using
entry
point
three
and
four
so
for
the
op-amp.
We
did
follow
the
entry
point
three
so
that
we
can
have
the
exact
same
placement
as
in
the
manual
and
then
for
the
powertrain.
This
is
something
I
mentioned
earlier.
E
So
the
goal
is
to
minimize
strain
and
sources,
and
so
this
message
as
much
as
possible
using
as
many
tracks
as
possible,
the
top
right
figure
shows
again
compares
the
layout
design
time
of
the
manual
effort
and
then
the
effort
put
in
to
realign-
and
here
again
we
can
see
7.5
x,
reduction
in
the
effort
involved
and
on
the
bottom
right.
We
have
some
selected
set
of
measured
results.
E
The
left
figure
is
showing
the
load
regulation
in
terms
of
the
volts
per
milliamp,
and
here
we,
the
generated
layout,
is
actually
performing
better
than
the
manual
and
on
the
right.
We
have
the
settling
time
with
the
maximum
current
step.
Here,
the
generated
layout
is
slower
than
the
manual,
and
this
is
mainly
because
of
the
flexibility
that
mask
designer
has
right.
So
here
you
can
see
easily
the
blocks
do
overlap
in
the
manual
layout,
but
in
the
line
we
do
actually
follow.
E
So
to
summarize
so
far
we
have
demonstrated
it
and
get
silicon
proven
results
on
power
management
circuits
and
right
now
we
are
working
on
enabling
the
p
values
it's
leveraging
t
cells
for
especially
passive
elements.
E
We
also
did
actually
exercise
a
line
on
a
more
advanced
synthetic
technology,
and
but
we
are
still
waiting
for
silicon
to
come
back
and
that
was
mainly
using
n3.3
and
iv.
So
in
this
case
we
are
now
working
on
enabling
more
automated
entry
points
on
that
node
and
we
are
still,
you
know,
continue
doing
research.
E
Another
line
of
research
is
generating
our
weakling
nail.
This
is
especially
a
harder
problem
in
advanced
fin,
fit
and
again
using
enterpoint.
Three
and
four
user
has
a
lot
more
control
and
it's
a
little
bit
easier
to
do
this
achieve
this,
but
there's
still
some
room
of
improvement
on
the
more
automated
entry
points
and,
finally,
we
always
try
to
improve
the
performance.
Layout
quality
basically
push
the
performance
with
a
smaller
area
footprint
and
that's
all
I
had
to
share.
B
Just
to
close,
I
want
to
kind
of
show
this
gallery
of
designs
that
we
have
over
here.
I
think
one
of
the
strengths
of
our
project
is
that
we
have
academia,
plus
industry
we
have
designers
plus
eda
people.
Ramesh
harjani
is
was
a
pioneer
in
analog
eda,
but
for
the
last
30
years,
or
so
he's
been,
focusing
mostly
on
design.
So
we've
had
a
lot
of
design
advice
from
him
and
also
from
intel
designers
who've
been
actively
testing
our
tools.
We've
had
a
set
of
chip
tape
outs.
B
B
This
is
a
vco
that
we
taped
out
to
them
in
march,
and
the
silicon
results
look
very
good,
so
we're
going
to
be
publishing
those
in
the
fall
and
aside
from
that,
as
I
mentioned
before,
the
call
started
we're
in
a
kind
of
a
very
close
coupling
with
the
michigan
team,
led
by
a
professor
wentz
loft,
and
we're
trying
to
generate
these
auxiliary
cells
that
are
required
for
their
design
methodology.
B
A
You
are
on
time.
Thank
you,
so
much
questions
from
folks.
A
So
I'll
start
with
one,
so
it
was
an
excellent
presentation.
It
looks
like
some
great
work
that
you
know
that's
ongoing
between
both
partner
universities
and
industry.
I'm
just
curious:
do
you
have
any
other
industry
partners
that
are
working
with
you
aside
from
intel
or.
A
So
that's
good
to
know,
I
think
I
know,
and
you
know,
since
I've
been
in
this
role,
I
I
do
hear
you
know
different
input
from
industry
folks
about
wanting
to
accelerate
the
analog
mixed
signal
design
space.
So
I
think
there's
a
lot
of
opportunity
here
right
and
that
certainly
would
be
a
be
of
interest.
F
Hi,
this
is
thomas
from
infineon.
You
mentioned
your
primitive
cell
library.
How
do
you
need
to
define
that
one
is?
Is
this
simply,
let's
say
some
python
code
or
how
do
you
define
your
layout
primitives.
B
F
Okay,
thanks
thanks
jones.
D
So
so,
for
example,
for
the
22
ffl
circuits
that
center
was
talking
about
the
primitives
were
built
by
by
you
know,
figuring
out
what
they
should
look
like
and
then
writing
writing
python
code
using
our
cell
fabric
foundation,
libraries
as
a
way
of
of
easily
constructing
and
placing
the
transistors
together.
Is
that
a
good
way
to
describe
its
honor?
Oh.
E
Definitely
and
the
idea
there
is
to
basically
capture
best
known
methods
on
that
node
right,
because
each
technology
has
might
have
different
effects
right
and
especially
as
you
go
to
more
advanced
nodes,
for
example,
layout
dependent
effects
become
more
prominent.
Then
there
are
certain
things
or
optimizations
that
you
can
encode
on
just
device
level,
transistor
array,
level
generators.
So
that's
a
but
again
that's
a
again
compared
to
writing
a
generator
for
an
entire
circuit.
That
is
still
significantly
less
effort,
but
in
a
one-time
investment
per
technology
now.
G
H
H
So
what
what
kind
of
effort
do
you
you
know
we're
talking
about,
because
all
these
three
technologies
have
different?
Let's
say
layout
methodologies
that
work,
and
you
know
it's
not
only
abstracting
or
let's
say
scripting
the
pdk
with
boolean
algebra,
but
also
the
layout
method
that
you
use.
H
B
So
I
can
give
a
high
level
answer
and
then
I'll
pass
it
on
to
sonar
because
he's
actually
done
this
for
a
few
technologies.
So
at
the
high
level,
one
of
the
things
that
we
do
is
we
basically
use
the
same
method
kind
of
overall
methodology,
regardless
of
the
node.
So,
for
example,
we
use
a
reserve
layer
model,
primarily
even
if
in
65
nanometers,
you
can
take
a
turn
in
metal
one
and
actually
connect
it
that
way.
B
E
Sure
so
there
are,
we
all
talked
about
the
primitive
generator
right.
So
that's
one
piece
of
it
face
of
it
is
basically
codifying
this
and
it
again
depending
on
the
technology.
If
let's
say
that
pdk
offers
t
cells
already,
then
the
effort
will
be
less
right
and
you
don't
have
to
draw
every
single
layer.
You
can
leverage
those
t
cells
that
would
reduce
the
amount
of
coding
involved
and
the
second
big
piece
is
engineering.
E
The
grid,
the
interconnect
rate
is
such
a
node
there's
only
unidirectional
grid,
and
that
is,
it
basically
requires
a
decision
of
what
pitch
can
width
to
be
used
for
that
technology,
and
typically,
there
are
recommendations
as
well.
You
know
again,
depending
on
the
note
on
what
are
some
recommended
wire
bits,
especially
for
analog
or
high
frequency
circuits.
G
I
mean
there
is,
there
is
a
I
mean.
The
overall
project
is
focused
on
fin
fence,
so
there's
I
mean
accommodating
that,
and
the
non-finfet
and
bulk
technology
has
a
decision
that
has
been
made
is
to
actually
put
the
priority
on
finfets,
and
so
there
is
a
little
bit
more
of
a
hit
on
the
bulk
technology,
especially
the
unidirectional
reserve
layer
issue,
but
in
general,
when
we
are,
we
have
done
rf
circuits
with
this
and
they've
actually
been
fairly
successful
in
65
we're
using
rf.
G
We
use
the
actual
rf
models
for
the
transistor,
so
it's
just
been
a
viable
technique.
I
think
at
this
point
we're
still
really
focused
on
the
finfet
side
and
need
a
little
more
effort
on
the
on
the
box
side.
B
E
Okay,
I
just
wanted
to
add,
like
in
terms
of
effort
right
again,
depending
on
how
demanding
that
node
is.
It
would
take
probably
two
to
four
weeks
to
engineer
the
grid
and
create
codify
the
primitive
generators
and
again
there
is
some
existing
code
open
source
which
shows
how
to
do
this.
So
it's
not
going
to
be
completely
writing
from
scratch.
It's
more
on,
take
what
is
written
and
then
maybe
customize
and
modify.
B
And
one
of
the
things
that
we
have
on
the
github
repo
is
a
set
of
mock
pdks
and
by
mock
pdks.
These
are
things
that
are
supposed
to
look
like
real
decays,
but
they're
all
taken
from
the
public
domain
literature.
So
we
have
a
12
nanometer
pdk.
We
have
a
22,
nanometer
pdk.
These
are,
and
when
I
say
pdk,
it's
not
a
complete
pdk.
There
are
no
spice
models.
These
are
basically
layout
design
tools.
F
B
The
whole
floor
is
independent
from
cadence
solutions,
so,
even
though
we
can
use
p
cell-like
structures
and
incorporate
them,
but
the
primitive
generator
basically
does
something
similar
to
what
a
p-cell
would
do.
B
So,
in
fact,
one
of
the
things
that
happens
sometimes
is
that
you
want
to
import
blocks
that
are
black
boxed,
so
you
don't
it's
a
designer
wants
to
use
something
that's
generated
from
outside
a
line.
So
what
we
need
to
do
is
go
through
a
step
where
we
take
that
block
and
put
it
on
the
align
grid,
and
once
that's
done,
it
can
be
used
as
a
black
box
and
again,
the
intel
folks
have
done
this
extensively.
F
But
when
you
now
talk
about
that
you're
currently
working
on
some
t-cell
support
or
more
p-cell
support,
therefore
for
for
resistors
or
passives
and
so
on
and
so
on.
When
you
talk
there
about
pieces,
is
this,
do
you
mean
this?
Let's
say
skill
pieces
that
you
get
from
the
pdk
for
cadence
there
or
are
there
pieces
only
programmable
sales?
Let's
say
in
more
general.
E
Yeah
I
was
referring
to
cadence,
which
also
parameterized.
H
E
So
again,
it's
it.
It
is
not
required
right.
The
you
can
still
use
the
line.
You
know
as
it
is
right.
I
was.
I
just
noted
that
again
for
especially
passes
it
could
if
they
are
available
right
and
we
also
make
it-
we
enable
it
to
flow
so
that
we
can
leverage
them.
That.
A
D
D
Now
that
is,
you
know
not
the
complete
set
of
of
tools,
so
you'll
have
to
go.
If
you
want
to
go
fabricate
it,
you
have
to
go
put
it
into
your
design,
environment
and
and
then
run
through
the
the
flows.
Now,
whether
that's
her
synopsis
or
or
canes
will
depend
on
on
your
manufacturer
right.
So
of
course,
of
course,
yeah.
B
D
You
you
want
them,
and
you
know
the
idea
of
our
drc's
is
to
have
them
lightweight
so
that
they're
still
fast,
but
they
cover
you
know
as
many
as
as
we
can
and
what
we
add
every
once
in
a
while.
We
need
to
add
a
few
more,
but
but
it's
pretty
good
right
now
in
terms
of
if
it
passes
our
internal
checks,
it's
likely
to
pass.
A
If
not
sakin
and
team,
I
want
to
thank
you
for
a
great
talk
today
and
also
some
excellent
work.
I'm
really
excited
about
looking
a
little
bit
at
it
myself.
I
was
particularly
intrigued
by
the
pattern
matching
problem,
knowing
that
from
earlier
lives
in
transistor
circuit
recognition
from
the
timing,
analysis
perspective
so
great
to
see
some
of
the
work
there
and
you
know,
looks
like
exciting
opportunity
that
you
all
have
provided.
So.
Thank
you
much.