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From YouTube: AWG / MOS-AK panel working group
Description
Silicon modeling panel discussion
A
A
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C
A
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F
C
Yeah
Eric
I,
don't
I,
don't
know
because
vladic
was
vladic
was
always
listed
as
a
as
a
panelist
and
so
were
some
of
the
others.
So
I
I
really
don't
know
why
there
are
some
of
these
discrepancies
with
the
zoom
so
to
speak,
but
thankfully
able
to
revise
these
here
on
the
fly.
So
that's
that's
good
news,
yeah
and
I
want
to
thank
all
the
panelists
for
making
time
to
come
today
and
also
for
the
audience
for
I
think
what
will
be
a
very
informative
session.
A
So
good
morning,
I'm
really
glad
seeing
outstanding
lineup
of
panels
today
and
growing
list
of
attend.
This
short,
it
will
be
a
very
informative
discussion
and
presentation
about
modeling
simulation
and
I
see
designing
particle
using
open
source
free
pdk
from
Sky
water
and
I.
Guess
there
was
a
request
to
slightly
change
agenda
and
I
think
did
you
Kevin
asked
to
be
first
because
of
your
time,
I.
A
Maybe
maybe
we
can
start
with
with
your
talk,
it's
a
update
on
standardization
efforts
and
I'm
sure
this
would
be
of
your
interest
and
then
we
will
or
right
onto
the
presentation
of
smooth
schedule.
So,
let's,
let's
begin
with
first
presentation
by
Kevin
on
his
contribution,
though
I
could
please
standardization
efforts.
Yeah.
H
H
H
I
moved
on
from
that
and
into
verilog
EMS
in
the
90s
and
90s
there
was
Cadence
and
there
was
it
analogy:
we're
trying
to
standardize
what
they
had
in
languages
and
kids.
His
Specter
stuff
became
very
loggy
essentially,
and
the
other
effort
became
vhdle
I'm,
not
really
sure
if
anybody
uses
vhdla,
but
it's
it's
still
there
and
has
the
advantage
of
being
an
IEEE
open
standard.
So
anybody
can
participate
in
vhdl
stuff
if
they
wanted.
The
IEEE
prologue
EMS
should
have
combined
with
verolog.
H
Ies
came
in
that
was
actually
super
long
at
accelera
and
they
sort
of
forced
the
way
through
to
IEEE,
without
incorporating
very
long.
Ems
and
Cadence
were
dragging
their
feet
on
the
thing
so
system
burolog
ended
up
at
IEEE
and
verlog
EMS
kind
of
got
abandoned
at
accelera
and
sort
of
he
sort
of
ran
along
until
you
know,
somewhere
around
2014
or
something
where
there
was
a
sort
of
a
final
version
with
some
broken
stuff
in
it.
H
So
it's
a
system
verolog
arrived
at
the
same
level
as
vhdl
with
user-defined
types
A
few
years
ago,
but
has
the
same
problem
as
vhdl
that
they
have
not
been
able
to
work
out
how
to
get
multiple
types
on
a
net
and
getting
multiple
types
in
a
net
is
where
the
mixed
signal
stuff
comes
in.
So
we've
already
done
multiple
types
on
that
with
only
two
types
logic
and
analog
and
verolog
EMS.
So
what
I'm?
H
Currently,
working
on
is
trying
to
get
the
verilog
AMS
stuff
brought
into
system
error
log
and
make
make
that
work
for
any
kind
of
types
on
a
net.
The
the
problem
there
is
usually
the
the
system.
Burolog
standard
is
entity
only
so
mostly
the
Eda
vendors
playing
there
and
they
don't
actually
like
changing
their
software
much
so
so.
Basically,
you
need
to
pack
the
Committees
with
people
who
are
interested
in
actually
having
it
work
in
order
to
get
things
through.
H
Particular
it's
set
off
in
sort
of
the
wrong
direction
and
is
not
not
adjusting,
but
we
could
actually
fix
that
one
in
open
source
space
and
and
then
bring
it
back
in
as
a
phase
two
p247
thing,
if
one,
if
people
want
to
do
that,
p6087.2
was
doctored
by
the
same
people
as
2427.
It's
about
doing
stuff
in
analog
test.
One
of
the
things
about
analog
is
unlike
digital.
H
You
really
need
to
simulate
it
to
see
if
it's
going
to
work
so
there's
an
opportunity
in
simulating
testers
and
and
running
your
test
languages
on
the
simulation
to
see
how
things
go
and
again,
the
the
easy,
easy
sort
of
entry
point
for
this
stuff
is
sort
of
edms
which
is
common
to
everybody.
And
this
is
where
the
modeling
stuff's
coming
in
I'm
saying
the
opportunities.
H
Oh,
this
works
right.
You
know
things
I
think
people
are
interested
in
is
how
do
we
apply
AI
to
to
Eda
stuff
and
I'm?
Looking
at
like
a
lot
of
the
mixed
signal,
stuff
I
see,
you
know
the
math
and
the
event
driven
stuff
looks
like
neural
networks,
so
so
I'm
looking
at
a
lot
of
people,
building,
AI
accelerators,
which
basically
neural
network
math
machines,
which
could
equally
all
work,
as
you
know,
as
mixed
signals
simulation
machines.
H
There
is
it's
multi-vendor,
so
you
you
can't
just
use
Cadence
tools
or
synopsis
tools
or
Mentor
tools,
and
that
creates
an
opportunity
for
doing
sort
of
large-scale,
Open,
Source
stuff,
so
I'm.
Looking
at
you
know,
can
we
build
multi-simulator
systems
for
developing
chiplet
systems
and
optimizing
them
and
get
people
like
Facebook
and
Microsoft
to
back
that
effort
anyway?
That
was
one
where
we're
we're
trying
to
do
Hardware
software
co-design
and
with
AI
at
ocp
and
the
chiplet
stuff
and
high
performance
compute.
H
If
anybody
wants
to
hop
in
there
and
join
the
effort,
what
I
would
like
to
get
to
with
that
stuff
is
to
be
able
to
do
asynchronous
logic
rather
than
RTL.
That
again
requires
mixed
signal
simulators
rather
than
the
discrete
simulators
and
then
can
we
can
we
get
above
the
RTL
level
and
design
at
the
neural
network
level,
sort
of
asynchronous
FSM.
So
that's
that's
a
quick
summary
of
where
I'm
at
so.
If
anybody's
got
any
questions,
go
for
that.
H
Yeah
I
would
say
the
The
Proposal
I've
got
in
at
the
system.
Burolog
thing
at
the
moment
is
that
when
you're
trying
to
do
parallel,
processing
simulation
the
thing
that
you
want
to
communicate
between
the
simulators,
you
know
whether
it's
their
the
same
simulator
or
different
simulators
is
drivers,
not
signal
values.
H
So
none
of
the
Eda
vendors
do
that
stuff,
so
I
think
there's
an
opportunity
for
sort
of
high
performance,
Computing
simulation
stuff
with
open
source.
That's
fairly
easy
to
get
at
part
of
my
proposal
for
system.
Burolog
is
just
a
sort
of
high
level
methodology
for
doing
things,
and
you
know
be
interested
in
sort
of
filling
in
an
API
that
will
work
for
like
NG
spice
Zeiss.
H
J
H
So
the
way
this
thing
the
proposal
I've
got
at
the
moment
is
that
if
you
look
at
how
the
the
simulators
work,
they've
got
drivers
for
Nets
and
then
there's
receivers
and
I
did
a
thing
for
Zeiss
for
I
was
pulling
out.
Piecewise,
linear
signals
and
feeding
them
into
the
digital
simulator
and
back
and
and
the
the
sort
of
picture
you
want
is
that
for
all
the
simulators
involved,
there's
a
driver
with
a
waveform
and
the
waveform
is
kind
of
your
pwl
thing
and
there's
a
receiver
somewhere
else.
H
So
the
waveform
and
you're
trying
to
sort
of
get
values
from
one
to
the
other
and
within
the
system
dialogue
environment,
we're
trying
to
get
it.
So
we
can
do
driver
access
like
viralog
EMS.
So
you
can
see
that
waveform
and
then
you
can
use
VPI
or
pli
or
DPI
to
get
it
out
into
your
your
analog,
simulator
I've
done
a
couple
of
Integrations
with
you
know:
digital
simulators
and
spice
simulators
in
the
past.
H
So
it's
really
not
that
hard
It
just
fits
in
with
the
pwl
source
stuff
and
that
that's
part
of
the
proposal
to
system
verolog,
because
they're
trying
to
get
to
UVM,
EMS
and
they're
trying
to
get
to
system
C
AMS,
so
so
they
they
might
go
for
supporting
whatever,
whatever
I'm
trying
to
do
in
some
way.
If
anybody,
if
anybody
is
an
entity
company
member
of
IEEE,
if
you
turn
up
for
like
four
meetings,
you
get
to
vote
on
things.
The
only
downside
at
the
moment
is
on
the
system.
H
I
mean
the
idea
here
is
that
if
you
know
the
connect
module
stuff
in
very
long,
EMS,
I
I
invented
that,
like
in
95.,
so
basically,
what
we're
trying
to
do
in
the
moment
is
say:
okay,
let's
just
do
connect
modules
in
some
form
in
system
dialogue
and
a
connect.
Module
is
basically
just
a
module.
So
anything
you
can
do
in
a
module.
H
I
think
I
think
one
of
the
things
I
would
Zeiss
is.
You
know
it'd
be
nice
if
we
could
do
stuff
where
we
can
hack
at
the
circuit
as
we
go
so
some
ability
to
restart
and
that's
right-
the
p2427
stuff
comes
in.
If,
if
we
can
do
the
defect
and
there's
just
our
market
for
this
defect,
analysis
and
coverage
stuff
and
if
we
could
get
Zeiss
to
do
that,
then
we'd
probably
have
quite-
and
it's
not
hard
to
do
that.
One,
because
I
think
you
can
probably
switch
models
while
you're
running.
H
But
p2427
is
a
good
opportunity
and
also
the
1687.2
stuff.
It's
just.
Those
committees
needs
better
Direction,
but
there's
there's
definitely
pars
there.
You
can
leave
religion
and
say:
okay,
we
can.
We
can
make
our
tools
do
this
and
we
can
also
start
our
own
powers
IEEE
for
doing
things
and
just
create
our
own
standards.
H
Yeah,
so
it's
so
if,
if
you
know
how
the
simulators
work,
you
know,
Eric
can
probably
talk
about
this
more
you
know.
Space
simulators
are
the
large
Matrix
math
thing
a
fast
space
simulator
tends
to
be
small,
Matrix
math,
PCS
switching
or
are
the
hard
pieces
and
then
lots
of
event
driven
stuff
between
those.
H
So
so
something
like
you
know
what
we're
shooting
for
with
very
low
EMS
is
you
you
have.
You
know
accurate
models
of
analog
things,
you
know
event
driven
models
of
digital
things
and
you're
mixing
those
together.
That
looks
a
lot
like
a
neural
network.
You've
got
layers
such
past
messages
between
and
then
there's
Matrix
math.
H
So
my
in
my
main,
you
know
very
long.
Ems
would
be
a
perfectly
good
language
for
describing
a
neural
network.
You're
doing
a
shorthand
for
the
math
in
there
circuits
are
circuits.
Don't
really
need
a
lot
of
precision
in
the
models
which
is
like
neural
network
stuff,
they're,
always
trying
to
cut
down
the
the
size
of
the
mayor.
H
F
So
there
I
will
comment
that
there's
a
there's,
a
whole
field
of
research
in
you
know
physics
and
form,
neural,
Nets
and
attend.
You
know
people
attempt
to
discover
models
by
from
data
and
a
lot
of
you
know,
depending
on
what
sort
of
activation
functions
you
use
and
stuff
like
that.
Neural
Nets
can
often
resemble
a
discretized
differential
equation,
and
so
we've
done
a
bit
of
research
in
that
area.
F
My
Talk's
not
really
about
that,
but
we
have
a
we've,
had
a
couple
projects
at
San
Diego,
where
essentially,
we
often
have
some
weird
physics
we
need
to
model
and
it
takes
forever
for
the
physicists
to
figure
out
a
model
for
it
and
we
have
data,
and
so
if
we
can
just
sort
of
take
the
data
and
then
apply
some
data-driven
technique
like
neural
Nets
to
it
and
create
a
model
quickly.
That's
a
big
win.
Yeah.
H
H
G
H
H
F
A
G
A
F
I
F
G
I
G
F
F
F
You
know
they've
they've,
basically
created
a
set
of
files
that
are,
you
know
for
one
of
the
two
common
commercial
simulators
and
the
main
two
are
age,
spice
inspector,
and
so
you
know
for
another
simulator
to
be
compatible
with
a
pdk.
That
means
that
you
really
need
to
be
compatible
with
the
you
know,
the
the
net
bus
languages
of
at
least
one
or
possibly
both
of
those
commercial
simulators,
and
so
that
actually
implies
lots
of
things.
F
You
know
you
have
to
have
all
of
the
right
device
models
available.
You
have
to
have
all
of
the
right
analysis
types
available
that
somebody
might
want
to
use.
You
have
to
have
good
expression
support.
You
have
to
support
the
same
syntax,
hopefully
you'll.
You
know
some
of
these
modern
pdks
are
really
complicated,
so
you
need
to
have
a
parser
that
performs
pretty
well
and
can
digest
the
massive
number
of
files
that
a
pdk
might
have
and
do
it
fairly
quickly.
F
So
I'll
be
talking
about
all
of
that
to
the
extent
that
I
have
time
and
I'll
give
a
little
bit
about
what
zeiss's
current
status
is,
is
a
fairly
important
priority
for
us.
Now,
although
it
hasn't
always
been
so,
as
some
of
you
may
be
familiar
with
zeites,
we
started
writing
Zeiss
a
little
over
20
years
ago.
F
F
One
sort
of
intermediate
thing
that
worked
on
as
a
atlas
translator
that
we
call
XDM
and
I'll
talk
about
that
a
little
bit
later.
Another
thing
that's
new
to
Zeiss.
That
was
we
were
just
discussing
in
the
last
talk.
Is
we
have
a
python
model
interface
which
allows
people
to
do
to
develop
ml
based
models?
You
know
using
tensorflow
or
pytorch
or
whatever
Library
they
want
in
Python
and
then
to
actually
execute
those
models
synthesize
that
list
and
just
call
them
from
there.
F
F
Maybe
we
could
use
a
database
method
to
develop
models
using
ml,
so
we've
had
a
few
or
we
have
a
few
ongoing
research
projects
on
that
topic,
see
other
things
about
Zeiss
we've
been
open
source
since
2013,
starting
with
like
6-0
we're
under
the
GPL
version
three
license.
Our
most
recent
release
was
7.6
that
happened
last
month
November
and
we're
trying
to
do
releases
every
six
months,
but
also
you
know
if
people
are
impatient
and
they
want
to
get
code,
changes
that
happen
in
between
releases
we're
also
GitHub.
F
F
So,
like
most
spice
emulators,
we
support
a
lot
of
the
standard
analysis,
types
that
you
see.
Anxiet,
noise,
AC
Etc,
there's
a
number
of
slightly
slightly
more
exotic
methods.
We
also
support
like
harmonic
balance
and
adjoint
sensitivities
and
polynomial
chaos
methods.
Those
I
think
are
a
little
more
unusual,
at
least
in
the
open
source
domain,
but
mostly
I
mean
most
of
the
sort
of
standard
techniques
are
what
people
who
are
running
pdks
with
wine
use.
F
So
we
do
have
support
for
those
I'm
going
to
say
a
little
bit
about
zeiss's
parallelism
and
mostly
to
sort
of
set
some
context
for
some
of
the
parsing
discussion.
So
there's
sort
of
three
parts
of
the
problem.
So,
on
the
right
hand,
side
you
have
a
flow
chart
showing
what
a
transient
simulation
of
Zeiss
would
do
or
any
simulator
would
do.
F
There's
sort
of
a
nested
set
of
solvers.
So
there's
a
time:
integration,
Loop,
there's
a
nonlinear
solver
inside
of
that
Loop
and
then
there's
a
linear
solver
inside
of
that
Loop
and
before
all
that
happens,
you
have
to
set
up
the
problem
and
that's
where
netlist
parsing
comes
in
and
so
I
think.
For
a
long
time
we
really
only
focused
on
optimizing
the
device
evaluation
and
when
you're
solved
parts
of
the
problem
and
that's
those
are
the
two
boxes
inside
of
the
loop
there.
F
But
we've
also
seen
performance
issues
and
parsing,
so
even
to
digitalize
that,
as
we
possibly
can
and
actually
the
parallel,
the
parallelism
that
we
apply
to
device
evaluation
actually
starts
during
parsing,
because
the
essentially
well
I'll
get
to
this
in
the
next
slide.
But
but
basically
we
try
to
distribute
devices
before
they're
even
fully
set
up
and
then
and
then
allow
as
much
of
the
setup
to
happen
on
all
the
individual
processors
as
possible.
F
F
F
We've
applied
subsequently,
where
we
try
to
wait
devices
based
on
how
expensive
they
are
so
so
we
also
can
do
device
waiting,
but
all
of
that
is
sort
of
determined
actually
during
parsing,
because
we
don't
even
want
to.
We
don't
even
want
to
set
the
devices
up
before
they're
communicated
we
just
want
to.
We
just
want
to
send
tokens
describing
the
device
to
each
person.
So
that's
where
the
parsing
comes
in.
F
F
It's
basically
flexing
and
parsing
things
that
don't
really
have
a
parallel
distribution,
so
either
stuff
that's
needed
on
products
only
on
proc0
or
stuff,
that's
needed
on
every
processor
and
then
we're
also
Gathering
statistics
on
that
pass
to
help
figure
out
how
to
do
the
parallel
Distribution
on
the
second
pass,
and
so
on.
The
second
pass,
and
basically
we
know
how
many
devices
there
are
going
to
be,
and
we
know
how
we
want
to
distribute
them
and
so
on
that
pass.
F
Then
we
just
do
some
sort
of
minimal
licensing,
and
then
we
pass
the
tokens
around
to
all
of
the
different
all
the
different
processors
and
after
the
tokens
arrive
at
the
different
processors,
then
the
rest
of
the
parsing
happens
and
the
rest
of
the
device
set
up
maps.
So
partly
for
this
reason
it's
been
you
know,
because
the
parallelism
is
kind
of
embedded
in
it.
That's
made
sort
of
refactoring.
The
purse
are
kind
of
kind
of
difficult.
F
So
what
we're
gonna
do
some
in
the
near
future
is
replace
the
Lexington
parsing
phases
with
a
much
more
modern
style
watching
in
person,
and
that
should
enable
us
to
apply
different
grammars
a
lot
more,
a
lot
more
easily,
so
I'm
going
to
revisit
this
in
a
minute.
But
that's
that's
basically
the
general
idea,
so
here's
kind
of
a
high
level
slide
about
zeiss's
compatibility.
F
So
we've
kind
of
taken
a
two-pronged
approach
to
that
one
is,
is
to
continue
hacking
on
our
on
the
existing
parser
to
get
it
as
close
as
possible
to
h-spice,
because
zeiss's
syntax
is
not
too
different
than
h-vice
and
we
have
a
command
line
option
that
sort
of
enables
all
the
h-spice
related
syntax
that
we
can
that's
available.
The
other
approach
has
been
to
do
something
more
comprehensive.
We
want
to
like
I
mentioned
before.
We
want
to
replace
the
Lexi
and
parsing
phases
in
science
with
something
more
modern
inside
the
department
tool.
F
First
and
so
we've
been
developing
a
code
called
the
Zeiss
data
model
or
XDM,
and
that
one
actually
uses
a
more
modern
parser
generator.
It
uses
the
the
Boost
Spirit
parser
generator,
and
so
we
have
grammars
worked
out
for
several
different
file
formats.
Now,
right
now
it's
a
standalone
tool
which
basically
converts
net
lists
and
pdks
from
whatever
format
they're
in
into
something
that
Zeiss
can
can
run.
F
Let's
see
another
element
that
we've
had
to
work
on
and
I'll
talk
about
this
on
the
next
slide,
since
we've
had
to
completely
rewrite
the
expression,
library
and
I'll,
explain
why
that
is
in
a
minute
and
then
also
in
order
to
support
modern
industry
standard
models.
We've
been
using
the
adms
neurologic
model.
F
It
has
been
fairly
I've,
been
I've,
been
successful
in
getting
undisclosure
agreements
set
up
with
global
boundaries
in
the
past.
I
have
not
been
successful
with
gsmc,
so
so
that's
one
reason
you
don't
see
very
many
tsmc
pdks
listed
here
the
and
that's
also
a
reason
why
I'm
pretty
happy
to
see
there's
this
move
towards
open
sourcing
pdks,
because
that
just
makes
collaboration
a
lot
easier.
F
F
News
12
liter
PK
that
particular
pdk
had
enough
enough
expressions
in
it
enough
parameters
in
it
that
we
were
getting
expression,
trees
that
were
really
really
big
and
because
of
a
fundamental
design
flaw
in
the
old
expression
Library
there
there
I
think
there
was
like
an
an
end
to
the
third
sort
of
search
in
it
or
something
like
that
anyway.
So
there
was
something
in
it
that
was
really
really
inefficient,
and
so
we
had
to.
We
basically
had
to
make
a
change
and
we'd
had
a
lot
of
complaints
about
the
old
expression
Library.
F
So,
like
the
example
I'm,
giving
here
is
a
vco
circuit,
I
think
that
was
the
first
circuit.
We
tried
to
run
and
it's
like
7.1
using
the
old
library
I.
Just
it
just
never
got
past
person
and
with
z72.
Not
only
does
it
get
past
person,
it
runs
the
whole
thing
in
about
20
seconds.
So
it's
a
it's
a
pretty
big
Improvement,
let's
see
I
guess
at
the
bottom
here,
I'm
also
talking
quite
a
bit
about.
F
In
addition
to
expression,
libraries
there's
also
been
a
lot
of
improvements
in
the
Purser
performance.
Mostly
that's
had
to
do
with
just
making
much
better
use
of
hash
maps
and
much
better
use
of
not
storing
things.
We
don't
need
to
store
a
lot
of
times
when
you're
using
a
pdk,
there's
a
lot
of
parameters
that
aren't
actually
used
by
the
particular
circuit
that
you're
running,
so
we
throw
those
away
as
quickly
as
we
can.
F
Let's
see,
I
also
mentioned
model.
Compiler
is
a
very
important
to
be
able
to
run
all
of
the
industry
standard
models.
You
know
there's
a
handful
of
standard
devices
that
that
modern
pdks
tend
to
use
like,
for
example,
the
BSN
CMG
model,
and
the
way
we
get
that
in
designs
is
using
the
adms
model.
Compiler.
F
One
thing
we
discovered
when
we
started
running
with
the
decent
CMG
was
that
the
the
code
that
we
were
producing
precise
from
adms
was
extremely
slow
and
I
was
largely
because
the
eight
automatic
differentiation
library
that
we
were
using
was
was
slower
than
we
thought,
and
so
we
completely
rewrote
the
way
that
we're
doing
ad
in
the
back
end
of
adms,
and
that
resulted
in
now
in
code.
That's
about
as
fast
as
handwritten
code.
So
we've
had
a
really
significant
speed,
improvement
from
that
and
and
basically
that
was.
F
I
will
mention
that
adms
it's
been
around
for
a
long
time
and
we
were
happy
to
use
it,
but
I
think
we're
getting
to
a
point
where
I
think
we
want
to
try
to
use
something
else,
and
so
we're
sort
of
taking
two
approaches
here.
One
is:
is
that
there's
a
there's,
a
new
open
source
model,
compiler
called
openvaf,
and
so
we're
looking
at
that,
but
we're
also
internally
developing
our
own
model
compiler,
so
at
some
point,
that'll
become
available
and
that
hopefully,
will
work
a
little
better.
F
The
main
problem
that
we
have
with
adms
is
that
it
doesn't
support
everything
in
the
the
verilogy
standard
and
it's
fairly
hard
to
hack
on
it
to
to
add
features
to
it.
So
so
that's
another
activity,
oh
I,
wanted
to
make
a
few
notes
about
model
compatibility
for,
and
this
certainly
affects
the
old
pbks.
F
You
know,
there's
you
know
in
order
to
be
in
this
business
at
all,
you
really
have
to
support
all
the
industry
standard
models,
and
you
know
there's
been
a
lot
of
work
under
the
compact
model
coalition
to
push
standardization,
but
for
a
lot
of
the
older
models,
some
of
which
I
think
perhaps
predate
the
CMC
effort.
The
standards
are
less
clear,
so
some
recent
examples
for
us
is,
you
know
we
have
the
spice
3
diode
in
Zeiss,
but
most
simulators
actually
have
added
stuff
to
the
spice.
F
3
diode,
like
you,
know,
sidewall
capacitance,
models
and
stuff
like
that.
So
we
had
to
add
those
another
example
would
be
the
Berkeley
beats
in
three
and
the
the
spice
three
code
that
came
from
Berkeley
is
not
quite
the
same
as
what's
in
most
simulators,
for
example,
there's
some
geometrical
parameters,
so
we
had
to
add
those
you
know,
so
those
sorts
of
things
come
up
and
that
that
can
be
a
bit
of
a
headache
to
deal
with,
but
we've
worked
on
it.
F
Let's
see
so
as
far
as
making
Zeiss
compatible
with
pdks
I
mean
an
awful
lot
of
our
Focus
has
just
been
on,
in
addition
to
the
parsing
issues
within
adding
features.
This
is
kind
of
a
there's,
a
very
long
list
of
things
that
we've
added
recently
and
there's
a
lot
of
stuff.
That's
in
progress
as
well
and
in
the
interest
of
time,
I
think
I'll,
move
on
to
the
next
slide
here.
F
F
Essentially
we're
just
planning
to
rewrite
to
replace
the
the
sections
that
have
to
do
with
Lexington
parsing,
with
something
that's
much
more
modern
and
we're
still
discussing
exactly
which
parser
generator
to
use
I
use,
flex
and
bison.
When
I
reread
the
expression
Library,
the
people
developing
xcm
have
used
Goose
Spirits,
so
those
are
probably
the
two
beating
candidates
for
that,
but
either
way
I
mean
language.
Grammars
are
usually
specified
in
a
fairly
common
format,
so
so
we
should
be
able
to
use
either
of
those
I
think.
F
Another
thing
we're
planning
to
do
as
part
of
this
is
to
create
an
abstract
data
model
which
sort
of
sits.
You
know
after
the
parsing
is
done,
and
that
abstract
data
model
allows
will
allow
us
to
basically
store
the
state
of
the
of
the
problem
in
a
binary
format,
and
so
that
that
should
enable
much
faster
simulations.
If
you,
if
you
don't
need
to
re-purse,
then
that
was
the
message
that
should
enable
much
faster
simulations.
F
The
Azure
data
model
is
also
part
of
our
plans
for
making
Zeiss
a
bit
more
Dynamic.
So
it's
easier
to
dynamically
change
things
in
the
in
the
circuit.
So,
let's
see
I
think
oh.
This
is
just
one
example
showing
that
size
gets
the
same
answer
as
a
commercial
tool
on
a
this
is
on
a
sorry,
ADC
circuit
using
Global
foundries,
12
nanometer.
You
know
we
have
a
lot
of
other
examples
like
this,
but
but
basically
we've
managed
to
make
that
work.
F
Our
hope
is
to
get
this
to
work
without
having
to
do
any
file
translation
at
all
right
now.
It
still
requires
some
file,
translation
and
yeah
I.
Think
that's
about
all
I
have
to
say
about
this.
I
mean
I.
I
could
talk
more
about
the
AI
stuff
if
anyone's
interesting,
I
have
a
I
have
a
slider
two
at
the
end
here,
but
I
don't
know
how
much
time
we
have
so
I'm
happy
to
take
questions.
F
F
So
I
guess
one
thing
I'll
mention
is
we're
doing
message
passing
so
we're
not
technically
doing
threading,
but
as
far
as
the
load
balance
goes,
I
mean
we've,
we've
kind
of
experimented
with
a
lot
of
things.
I
mean
for
at
least
for
our
message.
Passing
structure
we've
generally
found
that
it's
better
to
if
you're,
looking
at
a
very
heterogeneous
circuit
like
what
you
might
see
with
a
post
layout
circuit,
where
you
have
you
know
a
large
number
of
mosfets
and
also
a
large
number
of
parasitics.
F
If
the
circuits
rather
rather
homogeneous,
then
it
can
be
fine
to
to
group
them
by
type
as
long
as
as
long
as
they're,
you
know,
relatively
similar
expense,
I
mean
I'm
guessing
from
a
Threading
point
of
view.
I
mean
a
lot
of
times.
It's
it.
You
know
you're
looping
over
your
device
types
within
your
within
your
load,
phase
of
the
simulator
and
so
I
could
imagine.
F
G
H
F
H
K
H
F
F
Yeah,
let's
see
so
Muhammad's
question,
are
you
planning
to
integrate
the
translator
in
this
yeah?
I
mean
this.
Hopefully
my
my
talk
answered
that
question.
The
we're
planning
to
well
we're
basically
trying
to
recycle
the
grammars
that
we
develop
for
the
translator
and
then
use
those
grammars
with
to
set
up
a
modern
lecture
and
parser
in
the
directly
inside
of
size.
So
so,
hopefully,
a
year
from
now,
or
something
like
that,
it
won't
be
necessary
to
run
the
translator.
It'll
concise
will
just
run.
F
Let's
see
comment
about
tsmc.
Yes,
that's
my
experience
as
well:
Experience
open
source
fireworks,
so
I've
been
interacting
with
the
skywater
community
of
Fairmount
through
their
slack
Channel
and
so
on.
So
most
of
the
people
in
sky,
so
I
guess.
First
of
all,
the
version
of
skywater
that
I
have
used
was
I.
Think
the
one
Tim
Edwards
converted
to
run
in
g-spice
and
Angie
spice
is
not
100
the
same
as
ice,
but
it's
it's
closer
than
what
I've
experienced
with
a
lot
of
other
pdks.
F
F
F
F
F
The,
although
one
thing
I've
observed
with
agevice,
is
I
think
sometimes
they're
blazing
fast,
because
they've
taken
they've
taken
some
shortcuts.
My
experience
compared
to
Specter
is
that
we're
pretty
close
and
I
think
that's
well.
Hopefully,
nobody
from
Cadence
or
synopsis
is
going
to
yell
at
me
about
this,
but
but
my
experience
as
Specter
is
it
tends
to
be
a
bit
more
accurate.
A
spice,
let's
see
here
so
Tim
has
a
question:
is
the
Ivor
logo
simulation
considered
a
valid
way
to
do
so
and
that's
sort
of
so?
F
Let's
see
so,
we've
developed
a
mix,
a
mixed,
a
mixed,
a
mixed
signal,
interface
for
Zeiss
I,
kept
it
when
I
say
mixed.
We've
developed
a
mix
signal
interface
for
Zeus,
and
it's
been
called
from
a
variety
of
digital
tools.
You
can
call
it
from
bear
log,
but
it
doesn't,
but
we've
also
had
people
call
it
from
like
Pi,
HDL
and
stuff
like
that.
F
Let's
see
question
from
Kevin,
can
you
reach
the
Parables
into
this
The
Matrix
Hardware?
Yes,
that
there's
a
fair
amount
of
there's
fair
amount
of
tuning
that,
if
we're
running
truly
in
parallel,
where
we're
doing
a
true
sort
of
you
know,
especially
when
we're
doing
a
both
the
device
and
Matrix
part
of
the
problem.
In
parallel,
there's
quite
a
bit
of
two
anyone
can
do.
F
B
F
A
It's
quite
that
early
morning
in
New
Mexico,
so
maybe
one
more
cup
yeah
so
I
think
we
have
to
kind
of
speed
up
the
three
more
presentation.
Otherwise,
sorry
we
will
go
beyond
the
allocated
time.
We
will
have
meddy
talking
about
his
experience,
using
open
source
CDA
tools
for
free
pdk
of
skywater.
Then
we
have
Matthias
Booker.
A
He
will
give
an
update
on
akv
and
its
implementation
into
open
source
tools,
and
the
very
last
talk
today
will
be
by
team
talking
about
his
work
on
skywater,
Library
compatibility
with
spines
and
your
Eric.
Your
address
couple
of
points,
so
there
will
be
a
continuation
of
this
discussion
before
I
will
give
the
flow
to
maybe
a
Rob.
Can
you
assign
Matthias
boher
as
panelist?
He
will
talk
after
midi
about
AKB
model.
A
A
D
The
the
idea
behind
the
workshop
was
initially
to
talk
about
how
we
can
improve
the
technology
design
Loop
here
that
we
discussed
with
Rob
as
part
of
the
chips,
Alliance
activities
and
but
I'll
go
through
a
little
bit
of
the
work
I've
been
doing
and
how
I
encountered
the
open
source
tools
and
how
we're
trying
to
improve
them
as
we
go.
So
the
talk
is
lower
in
barriers
to
chip
design
using
openfa
stock.
D
Opener
Facebook
is
a
framework
that
started
or
it's
a
color
called
re
of
fa
stock,
which
is
a
DARPA
program.
So
let
me
just
move
to
the
next
slide.
So
if
I
talk
started
with
the
open
road
and
other
tools
as
part
of
the
idea
program,
I
think
size
is
part
of
it
as
well.
It's
a
military,
University
and
the
industry
effort.
We
are
part
of
chips
Alliance
and
we
teamed
up
with
arm
and
Virginia
too,
and
we
Professor
winsloff
was
the
lead
of
this
project.
D
Here
we
have
a
couple
talks
and
chips
Alliance,
so
you
can
go
and
take
a
look
at
them
and
I
listed
a
couple
of
papers
we
had
throughout
the
program
over,
of
course,
the
program
we
have
successfully
tipped
out
to
a
good
number
of
socs
from
gf12
to
TSM
c65.
We
demonstrated
some
of
them
at
the
URI
Summit,
and
that
was
successful
and
as
we
you
know,
as
the
open
source
pdk
was
released,
we
started
taping
out
more
chips
in
skywater
and
experimenting
more
more
stuff.
D
But
before
now
we
are
labeling
ourselves
as
open
fa
stock,
which
is
open
source
for
the
autonomous
SOC
synthesis
Tool.
We
are
part
of
chips,
Alliance
I'm,
sharing
the
analog
working
group
with
Rob
and
we're
discussing
a
lot
about
how
to
make
an
AUX
generation
and
custom
circuit
generation
more
automated,
using
open
source
tools.
Now
we
are
funded
by
Google
nest
and
a
couple
other
people
and
in
our
framework
we
are
not
only
using
a
service
approach
but
we're
using
tools
like
GDs
Factory,
and
sometimes
we
call
a
lion.
D
D
As
you
all
know,
it
must
have
it
is
custom
and
require
multiple
iterations
from
schematic
entry
to
layout,
then
simulation
and
so
forth.
The
digital
flow,
however,
is
fully
automated
right
and
we
can
call
it
a
grid
based
flow.
So
the
idea
here
is
to
basically
take
what
would
otherwise
be
a
full
custom,
anode
layout
and
shoehorn
it
into
the
cell
based
digital,
automated
design
flow
methodology,
which
is
very
amenable
to
the
available
logic,
synthesis
and
placed
in
route
tools,
be
it
proprietary
or
open
source.
D
So
you've
heard
that
a
few
times
now
we
use
a
cell
based
approach
and
the
idea
is
basically
to
divide
and
conquer
the
experience
we
had
with
a
fully
automated
or
Custom
Custom
based
analog
generators
is
that
they
it's
very
hard
to
bring
them
up,
and
it's
it's
a
pdk
dependent.
So
it's
really
hard
to
come
up
with
a
test
case
and
Port
it
to
a
new
technology.
D
This
could
be
either
from
a
traditional
Sanders
Library
or
a
library
that
has
been
augmented
with
a
couple
of
cells,
and
we
call
this
access
distance
as
auxiliary
cells,
Rock
cells,
we
so
to
demonstrate
our
demonstrate
our
framework.
We
did
notified
a
couple
circuit,
diagrams
or
generate
or
analog
blocks
that
we
have
published
in
isscc,
blsi,
basically,
Flagship
conference
circuit
conferences,
all
these
structures
have
been
taped
out
before
and
published.
D
So
these
are
Legacy
designs
that
have
proven
their
results
on
other
nodes
and
I
highlighted
in
blue
the
example
of
auxiliary
cells.
So
for
your
for
designs,
XR
adcs,
the
ldo
stamp
sensors,
PL
and
switch
cap
dc-dc
converters.
So,
each
time
the
analog
functions
is
either
an
auxiliary
and
header
cell
power
switch
a
flying
cap,
a
comparator,
and
so
it's
usually
a
12
below
transistor
block,
and
that
is
easier
to
tackle,
especially
if
it
is
if
it
defines
the
the
analog
functions
of
your
design.
D
D
They
they
usually
take
a
day
or
two
to
make.
Based
on
the
Innovation,
you
want
to
make-
or
let's
say,
you're
working
from
Skyward
130
to
Intel
16.
You
don't
have
any
native
transistor,
for
example,
or
any
other
exact
exotic
devices
so,
and
that
requires
you
to
rethink
a
little
bit
your
your
your
sensor
or
any
other
block.
So
in
that
case,
what
we
do
is
we
try
to
I
could
accommodate
the
auxiliary
cells.
D
You
know
in
a
way
we
can
pour
the
design
to
from
a
skywater
130
technology,
which
is
a
much
older
technology
to
refined
technology,
and
that
has
been
working
fine.
We
just
recently
taped
out
Intel
16
chip
that
that
is
showing
really
good
PEX
results,
but
in
general
these
are
the
the
auxiliary
cells.
They
look
like
standard
cells,
they
are
12
transistors
below.
We
try
to
use
different
Frameworks,
for
example,
aligned
from
Minnesota
and
Intel
to
basically
automate
this
last
piece
of
openfa
stock.
D
It
has
been
a
little
bit
challenging,
sometimes
especially
when
we
go
on
on
Advanced
notes,
but
it's
still
it's
still
working
for
some
of
our
auxiliary
cells.
So
it's
I
think
it's!
You
know.
It's
a
trade-off
on
how
much
you
want
automation
versus
Custom
Design,
but
the
idea
here
is
basically,
if
you
are
able
to
Define
different
auxiliary
cells,
you
are
you
you
go.
D
You
are
going
to
be
able
to
generate
thousands
of
designs
and
that's
that's
actually
very
interesting
in
especially
in
the
open
source
tools
where
you
don't
have
any
license
or
requirement,
or
you
don't
pay
for
your
license.
So
you
have,
you
can
generate
thousands
of
hundred
thousands
of
designs
and
basically
come
up
with
an
algorithm
to
decide
which
design
is
is
best.
So
I
think
this
is
very,
very
promising
and
we'll
see
much
more
of
it.
D
D
So
fsap
relies
on
a
set
of
proprietary
tools
and
wrapped
inside
the
Cadre
flow
developed
by
around
Professor
Ron
drezinski
from
Michigan,
and
it
isn't
as
abstracted
layer
over
the
closed
tools,
but
now
using
open
source
tools.
We
we
are
heavily
reliant
on
Open
Road
among
other
tools.
Also
GDs
Factory
I'll
I'll.
D
Try
to
discuss
that
later
in
this
presentation,
but
there's
a
couple
other
tools
like
your
CCBC
for
logic,
synthesis,
Sherlock,
uhdm,
plugins
integrated
by
and
micro
and
Google
for
system,
dialog
support,
magic
net,
gen
and
K
layout
thanks
to
team
Edwards
who's
here
and
also
NG
spice
excise.
So
we
don't
really
have
a
full
support
of
size
yet,
but
I
think
that's
one
of
the
action
items
we
have
for
the
next
months.
D
Here
you
require
100
complexity
and
compared
to
the
initial
version
we
had,
which
is
fa
stock
1.0,
which
is
standard
cell
only
based,
we
had
minimum
constraints
and
digital
compensation,
so
that
was
four
years
ago,
and
what
we
try
to
do
is
basically
include
some
partial
constraints
of
the
of
the
digital
flow.
Like
fencing,
non-default
rules
voltage
domains
to
basically
accommodate
some
of
the
needs
for
another
design,
and
when
we
do
that,
we
swing
back
into
the
middle,
where
we
we
can
see
that
we
can
get
the
best
of
both
words.
D
So,
in
fact,
in
using
our
sales
digital
approach,
we
are
in
reality
within
the
extreme
complexity
of
trying
to
take
all
taking
all
the
pdk,
DRC
rules
that
comes
in
with
full
custom,
automated
layout,
like
routing
and
active
layer,
drawing
also
with
the
rule
of
Dimension
Returns.
The
time
required
porting
to
a
new
pdk
or
even
a
new
design.
Topology
would
essentially
make
an
automated
flow
or
full
custom
analog
generator
too
costly
to
make
across
pdks
and
test
cases,
and
we
we
have
seen
precedence
in
that.
D
So
I
think
we
have
here
a
sweet
point
which
I
fundamentally
believe
we
could
push
more
to
the
left
using
open
source,
tooling
and
Automation
and
I'll
discuss
that
later.
In
this
presentation,
here's
a
few
examples
of
what
constraints
would
look
like
for
a
PLL
where
we
gave
extra
attention
to
the
dco
block.
We
are
using
Python
scripts
to
structure
the
placement
of
the
of
fine
and
course
cells,
where
all
the
cells
are
sitting
tightly
on
fairly
wide
stages.
D
D
Another
example
is
for
power
regulation,
digital
audio,
which
taped
out,
which
shaped
out
in
different
Technologies,
including
Skyward,
130,
gf12
and
GSM
c65.
You
can
see
the
pre-pack
simulation
of
the
max
load,
current
versus
the
array
size
of
the
pmo
switches,
where
everything
looks
fine
and
smooth,
but
then,
after
running
the
design
to
APR
with
minimal
constraints
and
random
placement,
we
see
after
Prospect
simulation
that
the
max
load
current
takes
at
all
and
goes
way
down.
D
So
and
as
we
increase
the
the
array
size,
we
can
clearly
see
that
the
variations
and
resistive
effects
due
to
narrow
routing
or
minimal,
via
cuts
so
to
address
that
we
came
up
with
a
more
structured
placement
of
the
switch
array
as
long
as
well
as
fancy
in
some
of
the
cells.
We
also
did
automatic
pdk
parsing
of
its
metal
stack
info
to
calculate
resistivity
over
the
power
switch
power
Stripes
mesh.
D
D
These
are
the
measurement
results.
I'll
just
go
later,
a
higher
level.
I
don't
want
to
bore
you
with
the
details,
but
basically,
as
if
you
make
64
senses,
you
can
map
out
what
is
possible
in
this
technology
with
different
features
like
high
density
sensors,
you
can
squeeze
the
the
size
or
high
speed
you
where
you
can
have
a
better
inaccuracy
or
a
time
conversion.
So
this
is
really
good
for
foundries
to
experiment
in
their
designs
or
their
capabilities
and
sell
their
technology.
D
But
basically
we
got
really
state
of
the
art
results,
even
if
we
designed
semi-blindly
or
our
temp
sensor.
This
is
in
inaccuracy.
This
is
below
one
degree
C
in
our
inaccuracy,
which
is
state
of
the
art,
and
this
is
a
table
of
or
summary
comparison
table
of
how
we
compare
to
other
published
paper
in
isscc
or
cicc
or
jsscc,
but
I'll
share
this
slides.
D
You
can,
you
guys
can
go
through
this
table
if
you
need,
but
one
thing
I
want
to
bring
up
here
is
something
we
discussed
with
Rob,
which
is
the
technology
and
design
feedback
loop
and
how
we
can
make
how
we
can
take
the
chance
of
having
this
open
source
initiative
or
movement
happening,
and
we
can
improve
this
whole
Loop
and
make
it
you
know
available
to
everyone.
I
think
there
is
a
real
issue
between
tools
compatibility.
You
know
the
models
doesn't
run
if
you
run
the
closed
tools.
That
was
my
experience.
D
I,
don't
know
what
others
had,
but
I'm
not
able
to
run
a
simulation
using
close
tools
to
to
the
comparison,
so
I
had
to
use
the
properly
pdk.
To
do
my
analysis
here,
this
was
done
two
years
ago,
so
maybe
things
changed
I,
don't
think
so,
especially
on
the
model
size
model
size.
So
we're
working
on
that
there's
a
real
issue
with
the
quality
of
the
model,
so
we're
working
with
a
couple.
D
D
But
here
one
thing
I
want
to
note
here
is
that
even
if
you
design
blindly
it
wasn't,
you
know
it
was
for
a
reason,
because
this
is
what
English
spice
is
giving
me
in
terms
of
inaccuracy
and
we
are
getting
up
to
3
degrees
C
when
I
use
the
proprietary
pdk,
requests
and
close
tools,
I'm
getting
something
closer
to
what
I'm
getting
on
silicon,
and
it's
not
it's
still
not
great.
This
is
just
the
closest
I
got,
so
we
in
terms
of
power,
especially
at
-40
125.
D
D
Yep
so
yeah,
this
is
the
second
shuttle
we
didn't
stop.
There
I
mean
we.
The
the
model
issue
didn't
stop
us.
We
can
open
fa
stock
is
good
to
generated
a
wide
range
of
designs,
as
I
said,
so
we
can
actually
design
letter
silly
blindly,
but
we
can
when,
based
on
our
experience
on
and
previous
nodes,
we
we
kind
of
know
exactly
where,
where
we
target
our,
where
to
target
our
designs.
D
So
in
the
second
Shadow
here
we
we
taped
out
an
array
of
digital
adios
with
voltage
reference
and
unlock
buffers,
also
included
the
route
of
truss
called
open
Titan.
We
included
the
temp
sensor
second
version,
and
we
can.
We
included
a
couple
other
things
in
terms
of
flow,
to
be
able
to
do
this
work
here,
especially
on
Open
Road,
but
basically
this
we
included
the
voltage
reference
highly
trimmable
voltage
reference
to
account,
for
you
know
our
the
bad
models
and
variations.
D
We
added
TCAP,
VF
and
d-cap
cell
generator,
and
we
made
a
couple
different
switches
using
different.
You
know,
structures
or
flavors
like
native
and
mouses
or
or
pmoses.
This
is
a
simple
Leo,
but
it's
it's
kind
of
enabling
people.
They
can
reuse
this
and
show
the
capabilities
of
using
a
cell
based
approach.
D
D
D
I
want
to
go
into
the
details
of
the
needs
should
have
removed
these
slides,
but
basically
we
had
to
make
a
test
test
style
that
that
would
be
useful
for
people
to
make
new
models,
measure
them
and
you
make
new
models
and
I
think
that's
what
cool
card
is
doing
right
now.
This
work
is
done
under
the
umbrella
of
the
partnership
between
Google
and
nest,
and
we
taped
out
this
chip
on
mpw5.
D
But
during
this
use
this
step
out,
we
started
diversion
a
little
bit
from
the
cell
based
approach.
We
started
using
tools
like
GDs
Factory,
where
we
started
before
GDs
Factor.
We
used
open
road
to
to
do
this
swing,
oscillators
that
that
needs
to
fit
to
be
fit
needs
to
be
to
fit
the
40
by
40
footprint.
D
These
are
connected
to
the
bare
paths
and
there's
some
fencing
here
going
on
with
some
interleaved
placement,
where
we
use
the
python
to
do
the
interleave
placement
and
manipulation
of
the
the
files
we
taped
out.
This
is
using
openfa
stock,
so
we
were
able
again
to
Port
all
the
standard
sets
to
this
24
ring
oscillators
in
total
and
including
the
OSU
standard
cell
libraries
done
by
James
Steins
from
OSU
University.
D
This
is
the
the
structure
we
made
using
the
GPS
Factory.
This
is
made
using
Python
and
those
are
really
low
hanging
fruit
because,
but
you
can
do
what
we
notice
is
that
we
can
make
a
function
to
do
an
array,
placement
or
a
mesh
generation,
and
those
functions
are
kind
of
generate
because
you
can
just
make
it
you
take
in
the
dimensions
the
pitch
and
layers.
Then
we
can
reuse
that
for
different
blocks.
So
this
is
a
meme
cap
array.
D
So
at
the
end
of
the
day,
we
had
1400
pads
of
a
lot
of
transistors
and
this
is
the
resultant
that
died.
These
are
our
partners
from
this
adsr
and
cool
cat.
We
had
a
lot
of
other
people
joining
later
on
from
gwu,
Brown
and
CMU,
who
helped
us
through
the
stapas.
But
one
thing
I
want
to
note
here
from
this
these
shuttles
here
or
this
test
harnesses.
Is
that
as
we
went
from
mpw5
to
mpw
six
and
seven,
this
is
three
months
time
frame.
D
This
is
a
very
High
pace
of
taping
out,
but
we
still
could
manage
it
by
while
using
openfa
stock,
and
you
can
see
that
the
complexity
is
getting
a
lot
more,
a
lot
higher
as
we
go
through
the
shuttles
and
I'm
sure
in
mpw8
we're
gonna
tape
out
some
Quantum
current
standard
structures.
That
will
look
a
lot
more
complex
than
this,
so
this
is
great
to
see,
and
hopefully
we
can
have
more
adoption
and
interest
from
the
community.
D
So
this
is
what
openfa
stock
looks
like
today.
This
is,
you
know
just
this
is
not
an
up-to-date
diagram,
but
it
just
basically
shows
you
that
we're
calling
new
tools
like
GDs
Factory
and
we
call
it
python
apis
for
to
manipulate
def,
but
also
to
to
do
manipulations
in
GTS
Factory
as
well
or
massage
the
layout
to
get
a
better
performance
as
we
go.
D
A
Yes,
yes,
indeed,
a
great
presentation,
huge
or
collaborative
effort
and
all
what
you
presented
was
done
using
open,
Sound
Stones.
This
is
something
unique
and
I.
I
hope
always
appreciate
your
work
and
there
will
be
even
more
followers
exploring
the
same
path.
If
you
can
look
at
the
chat
window,
there
are
some
questions,
so
we
we
have
still
time
for
sure
two
or
three
more
questions
so.
D
D
Well,
I
mean
we
do
a
lot
of
when
building
up
the
the
generator
from
ground
up.
We,
basically
we
want
different
configuration
or
basically
just
porting
it
right,
so
we
run
different
sizings.
Usually
we
start
with
minimum
sizing
and
we
just
go
as
we.
You
know,
increase
the
size
with
small
steps
and
then
we
can
get
a
sense
of
the
direction,
but
the
whole
modeling
part
is
kind
of
automated.
So
you
we,
when
we
have
to
do
it
for
Sky
one
130
to
Intel
16.
A
D
A
A
I
would
be
willing
to
follow
your
path
and
we
can
draw
more
attention
to
open
source
tools
and
design.
Automatization,
definitely
I
think
it's
a
little
bit
question
on
other
topic
about
parameter
extraction,
but
maybe
maybe
this
this
question
by
sabayoki
we
can
address
of
flying.
We
do
not
have
any
presentation
on
parameter
extraction
at
the
moment,
but
maybe
following
talk
on
akv
indirectly
will
also
address
parametric
structure.
So
I
would
like
to
invite
a
nick
Marcus.
E
J
Thank
you,
hello.
My
name
is
Nicholas
macris
I
am
a
PhD
Continental
Technical
University
of
great
and
I
am
working
with
ISL,
forcing
gunship
and
still
conquer
by
David
development
and
modeling
I
will
present
you
today.
Our
work
from
Technical
University
of
great
regarding
TV3
and
I
will
present
you
some
introductory
work
having
to
do
with
the
give
it
3
and
then
this
price
integration
using
kdms
XML.
J
The
outline
of
this
work
is
the
following:
firstly,
we
will
discuss
it.
I
will
present
you
a
bit
some
things
about
the
qb3,
what
the
contributors,
some
very
versioning
version
history
and
any
new
developments
in
the
model,
then
I
will
present
you
the
very,
very
lucky
structure
of
the
model.
After
that,
we
will
present
you
the
phenomena
covered
by
aqb3.
J
What
is
going
on
about
the
integration
of
these
V3
and
the
usage
of
vq3
in
different
simulators?
Then
I
will
discussing
the
three
images
spies.
We
have
done
some
simulations
and
we
integrated
the
simulation
part
with
the
visualization
part
in
Jupiter
lab
tool
that
I
I
do
prefer
using
it
right
for
this
sort
of.
J
So
for
this
sort
of
work-
and
finally
I
will
present
you
and
our
conclusions-
aqv3
is
a
compact
most
transistor
model,
it
is
it
is,
it
is
used
in
analog,
RF
IC
design,
Special
Care
is
is
given
in
the
RF
and
noise
performance
and
modeling,
and
the
development
and
maintenance
of
pqb3
is
is.
Are
the
development
limitations
are
from
Technical
University
of
great
and
the
charts
based
approach?
Actually
what
what
what
it
provides
us?
J
Help
us
to
write
the
questions
that
that,
finally,
will
we
will
avoid
convergence
problems.
Equivalently
is
the
success
or
the
successor
of
akv
2.6
utilized
in
it.
It
has
been
used
in
various
Technologies
and
Commercial
pdks
several
model
variations,
and
we
have
made
several
model
variations
in
order
to
cover
different
r
d
r
d
Deeds,
and
it
has
been
distributed
to
this
side,
Cadence,
synopsis,
size
and
and
and
other
vendors.
J
J
J
J
The
phenomena
that
are
covered
from
between
three
are
basically
first
of
all.
The
core
model
like
which
is
the
physical
modeling
of
the
charges
and
the
bias
dependent
overall
capacitance,
the
number
of
the
non-quasy
static,
behavioral,
the
RF
Behavior
Mobility
impact
ionization
current
gate.
Current,
the
lateral
field
effects.
J
Velocity
saturation
and
channel
explanation
reversal,
Channel
effect,
inverse
narrow,
with
effects
the
edible
source
and
brains
are
sharing
hello,
pocket
implant
effects,
Edge
conduction,
geometrical
effects,
width
and
scaling
noise,
where
we
we
are
using
two
models.
The
first
model
is
the
standard
model
that
it
was
included
in
the
previous
versions
and
in
the
newer
version
we
are
we're
using
a
a
a
version
of
that
or
the
flicked
noise,
which
is
a
Mac
Warfare
hopes
and
drain
Source
access
noise
models.
J
J
J
The
the
extent-
and
we
have
some
externally
or
a
nice
second
way-
is
externally
loaded.
Very
lucky
code
include
using
an
include
statement
in
the
model
card
which
is
actually
compiled
into
a
certain
Library
during
the
simulation
time
again,
I
think
usually,
the
MS
XML
like
in
Spectra
in
HP,
is
of
sim
or
in
quarks,
where
we
have
used
ekb3
some
some
forms
of
vq3
for
for
educational
purposes
and
for
research
purposes.
J
The
Third
Way.
Is
there
a
brief,
combined
form
of
the
model
as
a
an
external
Library
which
we
have
used
in
summary
projects
using
the
compact
model,
interface
of
spectrum,
the
possible
limitations
and
issues
regarding
the
use
of
adms
XML?
Is
that
sometimes
not
all?
The
features
are
supported
like
in
NC
spice
that
where
we
cannot
that
the
verilogy
model,
the
the
process
of
of
the
translation,
does
not
produce
any
noise
noise
files,
and
when
you
use
you
are
using
different
simulators.
J
J
There's
usage
of
what
version
was
actually
almost
almost
dedicated
the
for
experimental
and
teaching.
It
was
oriented
for
experimenting
now
in
order
to
to
use
the
new
version
of
the
atv3
and
we
try
to
cooperate
it
in
the
spice
version
3.8
over
here.
We
have
some
some
details
about
the
process
we
have
to
do.
J
In
order
to
recognize
the
ATMs
XML
that
there
is
a
file
over
there
that
there
is
a
model
that
it
is
called
hb3
and
in
order
to
extract
the
in
order
to
extract
the
the
code,
the
atv3
noise
dot
C
is
generated
in
order
to
to
compile
the
in
order
to
including
the
copulation.
They
give
me
three
noise
dot
C
file.
We
need
to
further
edit
anti-spicemic
file
and
modulate
it
dot,
cxml
files.
And,
lastly,
we
edited
Dev
dot
C
in
order
to
to
the
the
simulator
to
get
the
model
information.
J
The
inp,
though,
do
MP
and
D
dot
C,
which
is
the
file
well,
where
you
say
which
level
you
will
will
which
level
number
you
will
use
for
this
model
and
the
yeah
and
the
inp2m.c
file,
which
is
actually
the
parsing,
the
the
parser
that
recognizes
that,
when
a
in
the
line
when
the
line
starts
with
the
name
means
that
it
is
a
mosfet
and
that
they
give
me
three
is
a
type
and
device
for
experiment,
experimentation
and
purposes.
We
have
integrated.
J
So
the
the
all
whole
process
was
done
in
Linux
Mint.
We
have
generated
link,
Standalone,
executables
and
with
those
executables
with
that
way,
and
you
will
I
will
explain
why
using
a
cross
compilation,
the
the
idea
was
that
it
would
be
nice.
You
know
to
have
a
more
interactive
way
to
to
simulate
the
to
make
simulations
with
the
chemistry.
So
we
used
the
Jupiter
lab,
which
is
which,
which
provides
a
quick
and
easy
visualization
of
the
simulation
results,
and
we
it
can.
We
have,
we
are
easily
manipu.
J
It
is
easy
for
us
to
manipulate
the
data
that
are
the
simulated
data,
so
we
use
Jupiter
lab,
but
in
order
to
to
to
run
density,
spies
and
check
their
lab,
it
has
to
be
in
bus
mode.
So
if
you,
if
you
are
running
the
inbox
mode
by
the
executable,
you
have
to
to
exclude
the
GUI
from
the
compilation
and
the
libraries
that
we
used
for
the
results
out
there,
I
will
show
you
in
the
next
slides
are
a
multiple
clip
from
plotting
her
pandas
through
data
manipulation.
J
J
Then
we
have
a
function
which
actually
makes
the
simulation
and
makes
a
which
actually
modifies
the
simulation
file
every
time,
for
let's
say
with
rain
or
for
the
bulk,
the
bulk
potential,
then
it
is
written
in
the
in
the
disk.
Then
it
is
executed
using
at
the
end,
the
spice
ER.
The
data
are
retrieving
by
using
the
spice
eye
library
and
then
using
the
data
frame
we
can
take
and
take
the
the
simulated
data
and
this
routine.
Actually,
what
this
does
is
the
plotting.
J
Simulation
was
a
simulation
of
by
DVD
versus
versus
Brigade,
for
a
different
bulk
values
and,
as
you
can
see,
the
routine
is
very
easy,
modified
and,
and
the
code
can
be
easily
modified
and
reproduce
the
the
simulation
results
and
produce
the
simulation
results
over
here
we
see
the
same
graph,
but
in
logarithmic
scale,
and
we
say
we
see
something
that
it
is
the
data
that
they
give.
You
three
has
in
a
very
for
a
well-locked
time,
which
is
the
Earth's
conduction
which
can
be
seen
over
here.
J
J
Atv3
has
has
been
embedded
and
used
in
commercial
and
open
source
simulators
for
for
many
years,
and
we
hope
for
many
years
from
now,
atv3
can
be
embedded
in
the
latest
anti-spice
3.8,
using
an
image
XML.
We
we
will
do
the
special
effort
in
order
to
to
make
the
noise
modeling
decoration,
the
combination
of
anti-spice
and
Python
and
Jupiter
lab
reveal
is
an
easy
way
to
visualize
and
manipulate
simulations
using
open
source
and
free.
Actually,
tools
with
this.
J
A
Thank
you
very
much
Nick
for
for
your
presentation
introducing
or
reintroducing
kkb
AKB
free,
modern,
showing
its
implementation
procedure
and
analyzing
its
performance.
So
I'm
also
happy
to
see
my
name
in
your
presentation
for
my
tiny
contribution
to
standardization
offer
of
efforts.
If
we
have
some
questions
from
from
the
audience,
so
we
we
can
briefly
review
presentation
now,
I
guess
the
main
question
will
be
about
timeline
for
you
to
release
akv
as
open
source.
So
what
the
estimates?
J
J
Let's
say
in
order
to
have
to,
we
will
need
some
time
in
order
to
to
continue
our
debugging
and
result
to
a
version
that
would
be
even
more
stable
than
the
there,
the
one
that
we
have
over
here
right
now,
and
so
this
is
something
that
Professor
bushel
should
a
good
answer.
Maybe
it's
not
it's
not
my
position
to
say
right
now,.
A
J
Yes,
it
could
be
actually
I
think
that
this
would
be
a
a
good
way
to
start
and
we
are
going
to
to
do
it.
But
it's
not
it's
not
right
now,
the
the
time
to
do
it.
We
are
in
the
middle
of
the
process
right
now
we
are
trying
to
find
Diamond
and
and
make
and
make
it
as
good
as
the
go
to
and
finalize
the
code
in
order
to
be
able
to
to
say
that
we
will
open
source
it
in
other.
J
In
other
words,
maybe
let's
say
that
it
would
be
as
a
version
like
the
code
will
be
ready,
see.
Let's
say
that
forensic
spies.
Maybe
we
could
provide
this
the
the
code
for
the
model,
not
the
value,
more
the
verilogy
and
be
light
Basic
4
or
version
three,
which
are
Incorporated
in
theater
spice,
but
we
will
be
there
in
I
think
that
we
will
be
there
in
a
while.
A
J
J
J
I
the
noise,
the
noise
model-
is
there
the
aqv3,
the
red
login
code
has
already
Incorporated
the
it
has
the
the
noise
model.
The
difficulty
is
not
the
the
open
source
as
open
source
the
difficulties.
This
is
the
fact
that
the
anti-spice
that
we
were
we
are
working
right
now
does
not
support
the
extraction
of
of
the
code,
which
will
make
the
the
simulation
of
the
noise
and
ready
can.
E
Maybe
if
I
can
comment
I'm
working
with
Pascal
on
the
open
web
compiler
and
then
this
bias
team.
We
are
right
now
almost
finished
with
the
open
web
integration
I
mean
everything
is
working.
We
are
working
on
documentation
now
and
we
plan
to
throw
out
adms
in
one
of
the
next
releases,
so
I'm
not
sure
how
reasonable
it
is
to
spend
lots
of
time
debugging
this
ancient
interface,
when
it's
gone
probably
beginning
of
next
year.
E
A
A
Yes,
I'm
looking
forward,
this
will
be
of
interest
to
all
by
this.
Let
me
close
Nico's
presentation
on
AKB
and
we
have
to
quickly
move
to
the
final
talk
team
will
give
an
update
on
on
his
work
on
spice
or
energy
spice
compatibly
for
free
Sky,
water
libraries.
This.
This
is
really
important
topic
to
discuss.
I
hope
that
also
Rob
can
can
extend
our
meeting
Beyond
two
hours
limit
so
team.
It's
now
your
your
presentation,
yeah.
I
It
so
it's
a
fairly
targeted
presentation,
I,
it's
a
fairly
targeted
thing
that
I
did
and
I've
been
asked
to
talk
about
what
I
did
for
doing
the
model,
conversion
to
NG
spy
support
in
the
skywater
Sky,
130,
pdk
and
I've
I've.
Never
done
a
presentation
for
this
before
so.
I
just
threw
this
together
and
and
pardon
me
for
not
going
full
screen
with
this.
But
the
last
time
I
went
full
screen
was
something
on
this
computer.
I
Yeah
I
figured
it
was
okay,
yes,
please,
yes,
so
the
idea
is
that
we
wanted
to
make
the
skywater
pdk
compatible
with
open
source
tools
and
at
the
time
that
I
was
doing
this
I
did
not
have
access
to
Zeiss
I.
Wasn't
that
familiar
with
Zeiss
Zeiss
was
in
early
stages
of
development,
so
I
was
pretty
much
ignoring
that
concentrating
on
NG
spies
and
I'm
very
happy
that
we've
been
able
to
work
with
Eric
guider
and
his
team
and
and
get
some
Zeiss
compatibility
going
with
that.
I
But
this
is
sort
of
predates
all
that.
In
fact,
the
the
first
indication
I
had
that
I
could
potentially
just
simply
take
a
specter
model
or
a
whole
Specter
library
of
models.
The
entire
pdk
and
convert
it
into
something
that
is
induced
by
is
compatible
okay
from
this
from
Thomas
Ben's
at
ethc,
and
he
has
this
repository
on
codeberg
and
he
presented
this
at
a
conference
back
in
Zurich
I
think
about
five
years
ago
or
so,
and
it
was
just
a
surprise
to
me
that
oh
is
it.
I
Is
it
that
simple?
This
is
just
some
Python
scripts
and
he
did
a
conversion.
He
was
doing
the
conversion
on
the
fly,
so
I
ended
up
not
using
this,
because
I
wanted
to
actually
create
a
version
of
the
pdk
that
was
completely
compatible
with
NG
spice,
whereas
what
he
was
doing
was
having
some
scripts
that
would
read
in
the
the
whole
specter
libraries,
as
you
did
the
simulation
and
then
convert
them
on
the
fly
into
something
that
you
could
plug
into
into
spice.
I
Is
the
problem
we
had
here
was
that
skywater
didn't
have
h-spice
models,
or
at
least
we
didn't
get
any
for
the
for
the
open
pdk
development,
and
so
I
was
stuck
with
the
fact
that
I
had
a
pdk
that
was
done
entirely
inspector
and
had
to
make
it
NG
spice
compatible.
Somehow
so,
I
was
responsible
for
putting
together
all
these
scripts.
I
That
was
like
a
sort
of
two-stage
thing,
because
by
the
time
we
were
hurrying
to
get
this
open
pdk
out
and
by
the
time
we
actually
got
it
out.
I
was
still
thinking
about
how
to
do
some
of
these
things
and
the
conversion,
and
so
not
all
of
the
conversion
made
it
into
the
open.
Pdks
and
I'll
show
you
where
that
split
is
and
what
what
I've
done
about
it.
I
So
here's
my
experience
with
converting
Specter
format
to
spice
format.
So
this
is
just
a
GUI
image
of
Specter
on
the
left
side,
ng-spice
compatible
on
the
right
side
and
I
probably
can't
see
all
the
details
of
it,
and
it's
not
important
to
see
the
details
of
it
here.
I'll
go
through
a
couple
of
examples
in
a
minute,
but
the
main
thing
is,
the
format
is
pretty
close.
I
There
are
definite
things
about
Specter
format
that
require
a
lot
of
bookkeeping
in
order
to
translate
them,
but
on
the
whole,
it's
more
or
less
compatible
and
that's
what
makes
it
possible
to
just
run
it
through
a
series
of
Python
scripts.
Now,
after
hearing
Eric
heider
talk
about
Zion
XDM,
my
suspicion
is
that
I
could
probably
take
something
like
XDM
and
replace
this
whole
thing,
and
it
would
work
much
better
and
much
nicer,
but
this
is
what
I
did
at
the
time.
I
Some
things
are
very,
very
simple,
such
as
Specter
has
portions
that
are
already
spice
compatible.
That
does
not
necessarily
mean
ng-spice
compatible,
but
you
do
need
to
track
where
it
says:
simulator
line
equal
Specter
and
do
certain
conversions
there
and
then
track
when
it
says
light
and
equal
spice
and
do
certain
other
conversions
there.
I
I
I
This
is
the
getting
into
more
complicated
stuff.
So
Specter
has
this
idea
of
an
inline
sub-circuit,
and
so
while
it
is
actually
possible
to
convert
such
a
thing
into
regular
spice,
so
you
find
this
thing:
inline
subcircuit.
It
is
declaring
some
sub-circuit
name,
which
is
the
equivalent
of
some
spice
model.
I
The
the
pins
go
in
a
list
in
parentheses,
then
parameters
are
listed
in
a
separate
line
with
parameters,
and
then
it
calls
the
device
which
is
this
is
the
oddest
thing
I
think
about
Specter
is
that,
instead
of
using
the
spice
names
for
components
such
as
M
for
transistors,
then
they
have
names
that
are
the
sub-circuit
and
I
think.
The
idea
here
is
that
they
can
recast
this.
I
If
you
want
in
some
cases,
you
may
want
this
converted
directly
to
a
sub-circuit
like
an
X
or
a
when
you're,
calling
it
a
spice
file,
or
maybe
M,
if
you're
doing
LVS
on
it.
That's
my
understanding,
but
it
makes
it
difficult
to
parse,
because
you
never
know
what's
going
to
show
up
on
the
line
here,
you
cannot
just
use
the
spice
level
component
names
further
down.
I
They
put
the
model
in
again,
it's
done
without
a
DOT
card
on
it
and
they
have
their
own
way
of
specifying
what
type
of
model
it
is.
Instead
of
looking
down
on
the
parameters
and
saying
oh,
it's
type
equals
54
whatever
it
is
for
a
decent
four
they've
got
another
name
here,
be
sim4,
puts
everything
into
a
brace
delimited
block
for
a
bin
that
goes
on
a
separate
line.
I
They
have
recast
the
usual
spice,
telling
whether
it's
an
inmas
or
pmos
to
some
different
nomenclature
in
or
p,
and
all
of
that
has
to
be
translated
out.
This
is
a
lot
of
just
a
lot
of
bookkeeping.
Some
of
it's
just
direct
translation.
Remove
the
parentheses
change
parameters
to
dot
param
other
is
gets
a
lot
more
complicated
with
the
you
know,
figuring
out,
where
the
model
been
here
on.
I
A
separate
line
goes
back
into
the
model
name
as
a
suffix,
so
other
complications,
here's
where
it
gets
even
more
complicated
they've
got
a
sub
circuit,
for
this
is
for
the
high
resistance,
poly
resistor
again
the
pins
go
in
parentheses.
You've
got
a
parameters
block.
This
parameter
block
has
C
comments,
nested
in
it,
the
plus
lines
which,
in
spice
normally
go
in
the
First
Column,
have
been
indented.
I
Those
things
have
to
be
figured
out.
In
this
case.
The
resistor
is
calling
a
model
normally
in
spice
when
you
call
a
resistor
with
a
model
you're
implying
a
semiconductor
resistor
and
therefore
you're
using
width
and
length
instead
of
R
for
resistance.
But
here
they
have
used
the
model
just
to
insert
the
parameters
for
the
temperature
coefficients
and
so
I
had
to
sort
that
out.
In
that
case,
you
don't
really
want
in
in
regular
spice
nomenclature.
You
don't
want
a
model
for
that
resistor.
I
I
So
that
was
that
by
that
time,
this
is
about
how
much
I
got
done
when
we
did
the
open
source
pdk
after
that,
I
got
to
the
point
of
the
pdk
was
done.
I
was
having
a
hard
time
getting
Google
to
take
pull
requests
on
it,
and
so
I
started
putting
all
the
stuff
that
I
had
not
gotten
around
to
into
open
pdks
and
it
just
patches
these
files,
as
it
creates
the
our
version
of
the
open
source
pdk.
One
of
those
is
handling
the
Monte
Carlo.
I
So
again
you
can
see
at
this
at
this
stage.
I
have
the
open
source
pdk,
as
the
Google
repository
on
the
left
are
one
that
I'm
doing
with
open
pdks
on
the
right,
and
they
are
almost
one
one
for
one.
So
it's
a
much
simpler
patch
job
here
where
in
Specter
you
get
these
statistics
blocks.
You
got.
Statistics
blocks
with
mismatch
for
mismatch,
simulation
or
process
for
Monte
Carlo
process
variation,
and
they
tell
you
what
parameters
to
vary
by
this
very
statement.
I
This
is
a
lot
of
complicated
bookkeeping,
because
the
statistics
block
may
be
in
a
separate
file
from
the
model.
That's
actually
using
the
parameters
being
varied,
so
you
have
to
not
only
do
bookkeeping,
but
you
have
to
do
bookkeeping
across
the
entire
file
system.
But
ultimately,
what
happens
is
that
somewhere
in
a
model,
you'll
have
an
expression.
The
expression
will
use
this
thing.
That
Specter
is
saying,
needs
to
be
varied
and
that
gets
replaced
with
first
off
in
a
gaussian
function.
That
is
recognized
either
by
it's.
I
That's
an
h-base
thing
and
a
NG
spice
thing
and
then
to
say,
I'm
going
to
use
that
or
not
use
it
I
precede
that
by
multiplying
by
a
parameter
which
is
either
0
or
1,
which
is
in
this
case,
MCM
switch.
It
says
if
it's
one
I'm
going
to
apply
it
to
gaussian,
if
it's
not
I
want
a
fairly
simple
way
to
con
control,
whether
you're
using
the
Monte,
Carlo
or
not.
I
The
main
thing
to
do
is
since
this
is
a
parameter
and
could
potentially
be
any
number
whatsoever
take
that
out
of
the
hands
of
the
users,
put
it
elsewhere.
I'll
get
to
that
in
two
slides,
so
the
other
one
was
for
the
process.
Statistics
for
Monte,
Carlo,
again
same
thing,
same
concept,
Specter
will
say:
here's
the
parameter,
here's
how
it's
varying
and
you
just
need
to
go
through
the
entire
file
system,
find
out.
I
A
I
A
I
Well,
clearly,
the
way
that
Zeiss
is
doing
it
with
the
XDM
interface
is
a
very
good
model.
It's
very
nice
to
be
able
to
say:
oh
Zeiss
will
just
pick
up
the
pdk,
no
matter
what
it
is,
whether
it's
Specter
or
or
h-vice,
or
NG
spice
and
run
with
it
I'm,
not
sure
how
long
it's
going
to
take
other
simulators
to
get
around
to
the
same
model,
but
that's
clearly
a
good
model
for
the
future.
A
I
Well,
it's
there
and
it's
useful
when
it's
needed,
as
because
of
the
way
I
ended
up
breaking
it
up
into
two
sections,
one
for
for
creating
the
pdk
and
one
for
patching
things
and
open
pdks.
It's
not
a
simple
system
or
a
single
complete
system
to
use
I
put
all
the
scripts
that
I
used
for
creating
the
pdk.
Those
are
in
openpdks,
but
it's
it's
just
a
floating
python
piece
of
code,
so
it's
not
particularly
well
integrated
would
be
nice
to
do
something
like
that.
A
A
D
Beyond
that,
there's
a
there's
a
whole
opportunity
here
right
like
watch
markets
with
semi-mador
doing
or
you
guys
are
experts
in
modeling
with
sadayuki.
You
know,
there's
a
there's,
a
real
need
of
defining
this
Loop.
Where
you
know
boundaries,
they
usually
have
the
structures
and
each
you
know,
recipe
or
changes.
They
have
a
new
model
that
is
released
or
based
on
the
customers.
They
generate
new
models,
so
I
think
we
could
automate
this
whole
thing
for
Skyward
130
as
first,
but
also
for
other
nodes
that
are.
E
H
I
I
mean
a
hacked
NG
space
years
ago
to
dynamically
reload
the
models
because
it
sort
of
came
up
and
when
you've
got
dozens
of
parameters
to
our
model,
that
can
all
be
different
things
and
the
model
is
really
inefficient.
So
I
thought
well
I'll
do
something
which
just
recompiles
the
models
and
everything
that's
constant
will
be
taken
out
when
I
see
the
actual
instance.
So
it's
not
hard
to
to
do
that
kind
of
thing
where
you
just
you.
E
H
H
B
D
Yeah
I
think
adding
to
that
is
you
know
this
whole
Loop
here
is
requires
people
from
modeling.
You
know
Eda,
you
know
like
simulators,
and
you
know
designers,
so
I
think
it's
were
before
you
know
saying
which,
which
is
good
and
which
is
bad,
basically
getting
together
like
in
this
Workshop
or
follow-up
meetings,
where,
through
the
analog
working
group,
maybe
and
Define
these
things
right
in.
H
E
A
B
D
The
good
thing
with
open
source
is
that
there's
no,
you
know
we
don't
have
to
follow
some
one
thing
right.
We
we
can,
things
can
be,
it
can
evolve
over
time.
So
if
you
see
that
something
doesn't
work
that
that's
definitely
going
to
change
over
time,
because
you
know
we
always
choose
the
path
of
least
resistance
right,
so
yeah.
H
You
know
you
well,
once
you
go
to
working
at
a
certain
level,
you
can
say
well.
This
is
good
enough
to
standardize
for
everybody
to
use
and
everybody
I
mean
there's
a
whole
number
of
IEEE
standards.
You
know
people
have
just
gone
out
and
done
it
as
a
standard,
but
nobody
really
uses
it.
You
know
so
yeah,
but
it
looks
more
official.
If
you
do
that.
G
A
Yes,
maybe
for
for
the
next
meeting,
we
can
kind
of
isolate
a
couple
of
or
identify
certain
flow,
but
with
couple
of
tools
and
see
how
whatever
data
information
is
going
from
one
to
another
tool,
yeah
what
is
missing
and
when,
when
I
talk
about
models,
I
I
talk
about
compact
models,
no
verilog
AIDS
accepted
language
for
compact
model
distribution.
So
we
need
tools
which
will
enable
compound
model
implementation
into
a
simulator.
A
Then,
if
we
have
a
modeling,
simulator
simulator
have
to
rate
or
accept
certain
Library
formats,
then
we
as
long
as
all,
is
at
transistor
level.
So
we
we
can
look
at
simple
analog
blocks.
If,
from
this
point,
we
are
moving
to
digital
design,
probably
we
need
to
look
at
I,
don't
know,
timing,
libraries
or
something
else
which
will
go
beyond
transistor
level
design.
So
we
we
need
and
I
guess.
H
Well,
I
think
I
think
one
of
the
things
one
of
the
changes
is
when
we
move
from
like
something
from
like
NG
space
to
Zeiss
is
we
then
have
a
C,
plus
plus
based
simulator
and
in
C
plus
plus
it's
much
easier
to
do.
Object-Oriented
interfaces
for
things
and
and
that
that
opens
up
opportunities
to
to
make
stuff
more
portable
and
unpluggable
I
agree.
D
H
H
H
You
know
particularly
for
mixed
signal
and
RF
type
stuff
and
the
AI
we
just
kind
of
need
to
be
able
to
sort
of
work
out
how
the
pieces
sort
of
fit
together
and
in
ways
where
you
can
do
plug
compatibility.
So
you
should
be
able
to
use
both
NG,
spice
and
and
Zeiss.
You
know
pretty
much
in
the
same
environments.
They
should
have
the
same
apis
for
their
modeling
and
dumping.
You
know
logs
and
things
like
that.
A
H
Much
I
mean
that's
one
of
the
major
problems.
I
have
is
that
I'm
sitting
in
an
environment
at
the
moment
where
I've
got
specter
and
the
guys
have
like
used
all
these
little
Specter
sort
of
virtuoso
features
that
mean
that
I
can't
I
can't
Chuck
Specter
and
use
a
faster
simulator,
because
it's
like
they're
the
the
non-standard.
Only
some
of
the
stuff
is
standard.
C
H
C
You
to
have
you
either
have
to
belong
to
si2,
which
is
not
cheap.
I
did
see
the
one
comment
there
relative
to
the
compact
modeling
Council,
which
is
great
that
they've
taken
that
on,
but
again,
that's
not
a
necessarily
a
cheap
body,
so
to
speak
for
different
players
or
entities
to
to
comment,
and
certainly
relative,
to
open
access
right.
It's
not
open
because
you
have
to
either
be
a
Cadence
customer
or
a
member
of
si2
or
most
likely,
but.
H
C
H
H
H
H
A
H
Know,
what's
actually
patentable
in
arms
either?
Well,
the
answer
is
nothing.
You
know
it's
like
they're,
just
like
hoping
that,
like
a
lawsuit
will
stop
people
doing
things
you
know
so
and
stuff
that's
been
around
for
as
long
as
Open
Access.
You
know,
there's
nothing
passionable
in
there,
it's
just
it's
just
trademarks
and
copyrights,
you
know,
and
you
I
don't
think
you
can
copyright
an
API.
It's
particularly
and
stop
people
using
it.
A
H
F
D
F
I
H
D
F
F
F
H
A
What
I
can
hear
it's
still
Worth
to
continue
discussion?
We
are
already
half
an
hour
beyond
our
location,
does
not
mine
and
maybe
to
facilitate
or
continue
this
discussion,
as
suggest
that
maybe
we
can
have
yet
another
similar
panel
discussion
just
before
Christmas
and
if
you
prefer
a
name,
a
recommendation
or
suggestion.
Maybe
together
with
Rob,
we
can
kind
of
create
short
list
of
the
the
main
point
to
further
discuss.
Yeah.
D
Other
than
make
sense
Braddock,
so
we
probably
before
meeting
again.
We
should
start
some.
You
know
something
we
can
build
up
next
time
and
you
know
I'm
pretty
swamped
till
the
15th
December
or
16th.
So
maybe
we
can
take
convene
after
that
in
a
smaller
committee
and
discuss
what
are
the
main
points
that
we
need
to
develop
or
expand,
and
then
we
can
call
up
on
the
different
panel.
A
A
A
Having
update
on
his
verilogue
of
system,
verlock
standardization,
then
Eric,
giving
update
on
Zeiss
and
support
for
commercial
libraries
and
syntaxes
I
really
appreciate
the
medi
stock
with
a
really
top
level
overview
of
Open
Source
Eda
tools
for
IC
Design
This
was
really
impressive
and
we
should
have
keep
expanding
this.
This
listing.
A
Nico's
son
has
presented
update
on
AKB
free
and
the
work
on
NG,
spice
implementation
and,
last
but
not
least,
the
team
shared
his
experience
on
the
the
library,
skywater
library
compatibility
with
Andrew
spikes.
There
were
of
high
interest,
I
really
appreciate,
and
today
too
thank
all
speakers
today
as
well.
All
participants
who
are
still
with
us
in
the
peak
we
were
more
than
30.
A
attend
this
within
the
meeting
and
now
I
think
it's
a
time
to
close
and
again
thank
you
very
much
to
Rob
supporting
organizing
today's
event,
all
contributors
panelists
for
the
presentation,
as
well
attendees,
who
were
very
strong
staying
with
us
still
the
very
end.
So
thank
you
very
much
and
if
there
will
be
update,
of
course,
we
will
keep
the
the
mailing
list
and
share
our
news
about
Adventure
panel
discussion
quite
soon
so
again,
thank
you
very
much
and
have
a
great
day.