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From YouTube: CHIPS Alliance - Analog Working Group - 2021-06-01
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B
B
A
B
A
B
Now
it
looks
like
very
good
work
that
you
and
your
team
have
done,
and
I
think
it
looks
like
a
lot
of
novel
ideas
that
have
been
applied
to
the
problem.
So
right.
A
Thanks
thanks
yeah,
my
students
are
awesome.
Oh
by
the
way
one
of
my
students
minji
leo,
he
also
joined
just
in
case
right.
You
folks
are
interested.
Oh
that's,
fine,
some
kind
of
demo,
you
know,
but
I
I
will
do
some
video
demo
right,
but
you
know
if
you
know
some
of
you
guys
are
interested
in
some
real
demo
right.
So
we
can
show.
But
I
guess
you
know
it's
it's
a
scripting
right.
Oh,
I
mean
yeah.
A
Yeah,
oh,
this
is
rob
manz
he's
a
general
manager
of
chip
alliance,
an
old
friend
of
mine,
hi,
hi,
rob
hi.
B
A
Yeah
yeah
actually
rob
had
a
big
team
in
oracle
right.
I
think
yes,
that's
true,
being
oracle
right,
so
that's
why
he
travel
here
pretty
often
and
yeah
good.
All.
It
is.
B
And
I
see
michelle
loud
as
I
invited
michelle
to
join
michelle
used
to
work
with
me
at
sun
and
oracle,
and
we
met
first
of
all
a
synopsis.
Many
years
back.
I
don't
know
if
you
can
hear
us
michelle.
D
B
Yeah,
we
should
have
a
number
of
people
joining
us
this
morning.
So
oh.
C
B
A
B
Yeah,
I
have
a
call
today
actually
at
five
o'clock
west
coast
time
with
some
folks
in
shanghai,
about
a
fpga
project.
5.
A
A
B
A
B
Yeah
now
we
we
have
a
number
of
different
interest
areas.
You
know
aside
from
different
implementations,
you
know
or
what
you
know,
whether
it
be
cores
or
architecture,
if
you
will
for
different
accelerators
or
different
interconnect,
type
of
protocol
or
cache
coherency.
We
also
do
work
in
electronic
and
electronics.
A
Okay,
great:
how
about
fpga
there's
a
recently
open,
fdga
thing
right,
start
right:
utah.
B
B
So
why
don't
we
go
and
get
started?
It's
just
it's
a
minute
past
the
hour.
I
think
we've
got
enough
folks
and
you
know
people
will
trickle
in
as
the
time
comes
along.
So
I
want
to
welcome
everybody
to
our
meeting
here
today
and
it
gives
me
great
pleasure
to
introduce
professor
david
pan
from
ut
austin
and
he's
gonna
describe
some
of
the
work
that
he
and
his
team
have
been
championing
in
the
analog
space
with
magical,
and
so
I
appreciate
it
so
david.
A
A
Okay,
all
right,
so
thanks
rob
for
the
kind
of
introduction
and
invitation.
So
I
think,
since
this
is
a
you
know,
relatively
small
audience
and
please
feel
free
to
ask
questions
if
you
feel
you
know
really
there's
something
which
you
need
a
clarification
instead
of
waiting
until
the
very
end.
But
of
course
you
know,
I
can
also
you
know,
exercise
those
questions
and
answers
at
the
end
right,
but
you
know
feel
free
to
ask
questions
in
the
middle.
A
I
might
not
check
check
the
chat
box
right,
but
I
guess
just
unmute
your
microphone
and
ask
so
I
will
basically
introduce
a
magical,
open
source,
automatic
analog,
icl
systems,
leverage,
human
and
machine
intelligence.
This
is
a
project
that
I'm
leading
at
the
ut's
team
for
analog
ic
valve
I'll,
give
a
little
bit
background.
I'm
sure,
probably
you
have
heard
about
that.
But
anyway,
here
is
my
outline.
A
I
will
give
a
brief
introduction
and
then
I'll
talk
about
some
overview
of
magical
and
then
I'll
describe
the
different
magical
components
and
then
show
some
magical
results
and
then
conclude
so
as
we
all
know
right
so
ai
and
all
this
you
know
there's
a
big
booming
right.
So
there's
the
abc
behind
the
algorithms,
the
big
data
and
the
chips
right,
which
is
really
the
hardware.
A
That's
where
we
are
mostly
working
on
right,
whether
it's
analog
circuits
digital
circuits
or
you
know
dedicated
ai
accelerators
so,
but
the
chip
design
manufacturer
has
a
lot
of
challenges
right
in
terms
of
power,
performance
area,
manufacturability
yield
and
so
on
so
forth
and
not
but
not
the
least.
You
know
the
design
cost.
Like
really.
You
know
also
kind
of
follows:
the
moore's
law,
you
know
from
older
technology
to
more
advanced
technology.
The
design
cost
nre
cost
really
increased
significantly.
A
So
that's
why
two
and
a
half
years
ago,
darpa
started
this
eri
initiative,
electronics,
resurgence
initiative
and,
under
that
there's
the
ideal
and
approach
program
which
basically,
I
think,
darpa's
vision
and
a
grand
challenge
to
the
research
communities,
how
we
can
have
a
silicon,
compiler
2.0
that
can
have
no
women
in
the
loop
24
hours
turn
around
time.
It
funds
many
projects.
I
think,
including
professor
andrew
khan's,
open
road
thanks.
A
I
think
I
see
andrew
in
the
audience
and
meanwhile
there
are
also
other
open
source
projects
for
analog
and
fpga
and
so
on
and
forth
right.
So
so
among
all
these,
of
course,
you
know
you
know
my
work
for
this
project
is
on
the
analog
ic
layout
aspect.
I
do
have
a
lot
of
work
on
the
digital
ic,
but
in
this
project
I'm
mostly
working
on
analog
ic,
analog
ic,
although
you
know
it
doesn't
have
like
millions
of
transistors
or
tens
of
units
right.
A
When
you
talk
about
digital
right,
it's
a
huge
design
scale.
However,
analog
design
is
very
complicated
and
in
a
sense
that
right
now,
mostly
still
treated
as
like
art
and
heavily
manually
designed,
but
although
they
are
like
for
the
entire
soc,
that
may
not
be
a
very
big
component,
but
in
terms
of
design,
effort
is
huge
and
also
analog
is
becoming
more
and
more
important.
You
know
with
all
this,
you
know
5g
and
medical
iot,
et
cetera.
You
always
have
to
communicate
to
the
outside
world,
and
the
real
world
is
mostly
analog
right.
A
So
that's
why
we
are
trying
to
kind
of
really
you
know,
closing
the
design
and
denial
automation
loop
for
the
american
ic
design
in
particular
loud
aspect,
physical
design,
any
question,
okay,
so
yeah
and
magical
is
a
project
that,
as
I
mentioned
right,
we
try
to
develop
a
fully
automatic
analog
layout
systems
and
we
have
already
published
a
bunch
of
papers
on
this
and
we
have
also
open
source,
magic,
1.0
and
so
actually,
before
even
we
started
the
darpa
project.
A
A
So
in
general,
right,
here's,
the
overall
framework
of
the
magical.
So,
as
you
can
see,
the
input
is
a
net
list
which
can
be
described
as
a
spice
netlist
or
spectrum
netlist
with
all
kinds
of
pdk
design
rules
and
the
output
is
a
gts2
layout,
which
then
you
can
do
all
kinds
of
you
know,
validation
and
evaluation.
A
So
the
big
chunk
of
the
magical
we
have
there
are
four
components:
one
is
for
device
generation,
there's
not
too
much
like
intellectual,
like
a
novelties
here.
The
reason
we
do
this
is
to
make
it
open
source.
You
can
definitely
use.
You
know
like
cadence,
of
a
chooser
et
cetera
to
do
that,
but
we
also
have
kind
of
you
know
open
source
version
for
this
academic
conversion,
and
then
we
have
layout
constraint,
generation
extraction
and
then
a
placement
and
routing
engine.
A
So
essentially
you
know,
as
you
can
see
with,
there
are
a
lot
of
algorithms
which
have
been
used,
including
you
know,
machine
learning,
ai
pattern
matching
some
deep
learning,
but
we
also
have
a
lot
of
more
conventional,
like
analytical
algorithms,
for
example,
placement
and
for
routing.
A
We
have
used
a
star
search
which
are
pretty
widely
used
for
digital
routing
as
well
right,
so
I
will
show
you
some
of
these
details,
but
because
there
are
a
lot
of
stuff
right,
so
I
won't
be
able
to
show
a
lot
of
technical
details,
but
hopefully,
as
through
this
talk,
you
can
get
a
good
overall
picture
of
magical
and
the
device
generation.
Basically,
once
you
have
the
the
size,
you
have
to
generate
the
primitive
you
know
which
will
be
laterally
used
for
placement
and
magical.
A
A
Essentially
you
can
do
a
block
level
synthesis,
but
you
can
also
integrate
them
into
different
hierarchical
level,
and
so
that,
like
like
this
is
a
pretty
advanced
adc
chip.
As
you
can
see,
you
can
do
each
building
block
level,
but
you
know
once
you
put
them
together,
you
can
still
have
all
this
nice
symmetry
structure,
etcetera
right.
A
So
all
right.
Let
me
now
show
you
different
components
for
magical,
so,
as
I
mentioned
right
so
first
we
have
this
parameter
parametric
device
generation.
A
Essentially,
you
know
my
students,
we
implemented
this
parametric
device
generation,
kernels
using
python,
actually
minge
he's
actually
in
the
audience
he's
the
one
doing
this
did
this,
and
this
is
a
correct
by
construction
and
while
we
construct
those
device
like
primitives,
for
example,
ammos
pmos
with
gartering
and
the
capacitor
and
the
resistor
etcetera
right,
they
are
all
drc
clean
and
lbs
clean
and
again,
as
I
mentioned
right,
so
there's
not
really
too
much
kind
of
intellectual
novelty
here.
A
But
you
know
we
have
also
made
open
source
so
that
you
know,
if
you
say
hey,
I
want
to
have
a
tool
that
is
not
dependent
on
a
commercial
tool
to
generate
layout.
You
can
actually
use
use
this.
B
A
Yes,
so
yeah
this
one,
but
we
have
within
different
parameters
right
so
while
we're
generating
this
device
so
the
design,
once
you
read
the
pdk
right
so
then
you
pretty
much
set
those
parameters.
Then
you
can
generate
those
right
so
for
different
design
rules
pdks,
you
will
set
different
parameters.
A
Okay,
thank
you
thanks.
So
then
the
next
big
chunk
is:
how
do
we
do
analog
layout
constraint,
generation
right
so
for
analog
layouts?
There
are
a
lot
of
constraints
right
and
most
important
constraints
are
so
called
symmetrical
constraints.
Essentially
right,
usually
you
would
like,
for
example,
this
net.
These
two
nets
need
to
be
symmetric,
and
this
transistor
and
this
transistor
need
to
be
symmetric
and
it's
also
false
right.
So
so
usually
we
mostly
focused
on
the
symmetrical
constraints
right
and
the
because
originally
the
darpa
requirement
is
that
hey.
A
You
know.
Your
net
list
is
a
unannotative
that
list.
So
basically,
you
just
have
a
flat
net
list
or
hierarchical
net
list.
But
you
didn't
say:
oh
this
net,
and
this
name
need
to
be
symmetric
and
so
on
so
forth
right
you
could
also
have
an
annotated
netlist
and
then
we
just
read
in
those
constraints
and
then
right
into
our
like
database.
I
mean
right
data
structure.
So
basically
you
know
we
have
used
different
techniques,
including
small
signal
analysis
and
also
using
some.
A
You
know,
pattern
matching
and
also
at
the
system
level.
We
have
done
some
iron
hierarchical
analysis
and
in
order
to
use
some
graph
similarity
again,
I
won't
go
into
details,
but
the
key
thing
key
takeaway
is
that
we
can
extract
those
basically
symmetric
constraints
for
the
nets
as
well
as
for
the
you
know,
active
components,
transistors
right
and
you
can
do
it
in
a
component
level,
very
local
scale.
But
meanwhile,
if
you
have,
you
know
big
building
blocks,
we
can
also
say
hey
this.
A
B
Yes,
but
so
that's
interesting,
so
the
requirement
from
darpa
was
was
an
unannotated
netlist
and
then
effectively
you're
deriving
the
constraints.
Based
upon
the
analysis
that
you
do
of
the
input
data.
A
Yeah,
based
on
the
input,
you
know
you
just
net
list
the
connections
right
stuff,
like
that,
you
know
all
the
signals
from
here
this
I
think
maybe
media
can
give
a
little
bit
detail
very
interesting,
but
essentially
right.
We
do
those
kind
of
analysis,
then,
based
on
the
signal
analysis
and
then
some
kind
of
pattern
matching
and
some
kind
of
graph
analysis
and
then.
C
A
Kind
of
figure
out,
when
I
mean
we
could
do
more
than
he
did
or
we
could
miss
some
right
because
but
in
general
right
we
found
the
you
know
we
can
find
those
and
is
in
particular
right
because
analog
circuits
they're
very
they
prefer
a
lot
of
symmetrical
structure
right
right,
okay,
thank
you.
Okay,
thanks!
A
A
So
our
placement,
as
a
you
know,
usually
when
you
are
dealing
with
placement
right,
you
have
global
placement
and
detail
placement,
or
I
mean
legalization
placement
right.
So
our
global
placement
engine
is
based
on
a
non-linear
programming
based
global
placement
engine
and
here's
the
overflow
right.
So
you
have
global
placement.
Then
you
will
do
detail
placement.
A
Our
detail.
Placement
is
based
on
linear
programming,
based
data
placement,
and
you
will
do
area
best
compaction
and
then
you
will
do
further
wireless
frequent
compaction
in
terms
of
the
global
placement
which
determines
the
overall
quality
right,
but
not
necessarily
totally
legal,
but
we
are
going
to
have
those
iterations.
A
Usually
you
know
global
placement
have
all
these
operations,
it's
a
nonlinear
and
then
you're
going
to
iterate,
and
while
we're
doing
this,
we
also,
you
know,
have
the
constraints
into
it.
So
that's
just
you
know.
If
the
cells
say
hey,
you
need
to
be
symmetric
with
certain
axes.
A
You
know
during
the
placement
we
want
to
make
sure
they're,
more
or
less
symmetric,
and
also
our
placement
can
also
tap
into
some
system
signal
flow
right,
as
I
think
a
lot
of
you
mentioned
right
so
usually
when
designer
design
analog
chip,
they
probably
know
how
their
signal
flow
needs
to
kind
of
go.
A
You
know
maybe
top
down
left
to
right
and
so
on
so
forth
right,
so
you
could
also
have
a
system
signal
flow
to
guide
the
placement,
and
we
found
that
you
know
later
on.
I'm
going
to
talk
about
it
right.
So
if
you
use
that
it
actually
can
get
a
better
performance,
okay,
but
this
part
right-
maybe
designer
provided
right
but
again
right,
even
when
we
are
talking
about
those
constraints
right,
so
we
have
automatically
generated
ones.
But
meanwhile
we
can
also
have
a
designer.
A
Then
yeah,
here's
just
some
examples
of
how
plasma
works
right.
So
at
the
beginning
you
know
it's
not
legal.
You
gradually
spread
the
cells
and,
while
you
are
spreading,
you
try
to
meet
the
symmetric
constraint,
as
you
can
see
here
is
the
center
axis
is
very
symmetric,
mostly
between
the
you
know,
this
this
left
and
right
and
here's
just
an
example
of
our
bigger
adc.
As
you
can
see,
it
has
a
pretty
nice
symmetrical
structure
and
the
placement
can
make
it
pretty
compact.
A
So
while
we
do
placement,
you
know
so
one
thing,
you'll
notice
that
you
know
usually
right.
How
do
we
deal
with
well
right
when
you
have
standard
cell?
Well,
it's
you
know
pretty.
You
know
for
digital
designs,
it's
pretty
straightforward
and
it's
automatically
taken
care
of
right.
But
for
you
know,
analog
designs.
You
may
also
need
to
generate
the
end
wells
right,
those
wells.
A
So
what
we
have
done
is
that
we
also
one
thing
that
you
know
usually
designer
automatically
draw
it,
but
we
actually
also
developed
some
machine
learning
algorithm
based
on
gain
right,
generative,
adversity
network.
Again,
I
won't
go
into
details,
but
basically
it
will
automatically
generate
the
wells.
Why
are
you
generous
of
wells?
We
use
this
again
here,
as
I
mentioned
in
the
title
and
human
intelligence
right.
We
have
a
lot
of
you
know,
design
data.
A
I
mean
this
well-generated
data
from
original
designs
right
and
then
we
we
will
change
and
then
we
can
automatically
generate
the
whales.
A
And
another
thing
is
that,
of
course,
when
we're
talking
about
well,
there's
also
well
proximity
effects,
and
this
is.
C
A
To
generate
the
well
right,
ideally,
you
would
also
like
to
you
know,
combine
this
well
generation
together
with
placement
and
because
by
doing
that,
you
could
probably
because
otherwise,
if
you
just
generate
the
well
also
general
placement
and
do
well
and
then
as
the
post
processing
steps,
you
know,
your
placement
may
be
suboptimal
and
then
you
have
so
ultimately
you
may
like
to
have
this
loop
right.
So
actually
we
have
some
ongoing
work
on
that
right.
A
So
another
thing
related
with
placement
is,
like
you
know,
of
course
you
know
when
we
are
doing
placement,
so
usually
right
even
for
digital
right,
so
you
mostly
only
consider
you
know
main
area
and
wireless
right.
So
those
are
the
basic
objective
you
would
like
to
minimize
right,
but
the
wire
lens
may
not
be
enough
to
reflect
the
analog
ic
performance
right.
Of
course,
wireless
is
still
you
know.
A
The
first
order
is
very
important,
no
matter
whether
for
digital
analog,
because
if
you
have
too
much
wireless,
your
parasitic
will
be
terrible
and
then
delay
power,
or
is
that
fat
right,
but
still
right
analog
has
its
own
kind
of
performance
magics.
So
sometimes
you
know
like,
like
those
noise
and
other
you
know
different,
you
know
cmr
and
offset
or
all
kinds
of
metrics
right.
A
So
you
know
if
you
have
a
two
layers
with
similar
wireless,
but
they
may
have
very
different
post
layout
performance
in
terms
of
those
you
know
analog
metrics
so,
but
to
do
those
kind
of
simulation
it
could
take
a
lot
of
time.
Let's
say
you
know
if
you
have
two
layouts,
how
do
you
know
this?
One
is
better
than
the
other
or
one
is
not
as
good
as
the
other
right.
It's
pretty
hard
to
say
right.
So
that's
why
we
hope
to
also
have
some
placement
quality
prediction.
A
Let's
say
without
running
detail
the
post
layout
extraction
simulation
and
then
you
can
directly
get
the
placement
quality
prediction
post
layout.
So
one
nice
thing
of
our
magical
is
that
because
we
can
automatically
generate
you
know
many
many
many
different
layouts.
You
know
during
our
placement
right
we
can
adjust
the
net
net
weight
and
other
things
right.
We
can
actually
generate
thousands
of
tens
of
thousands
different
males
very,
very
fast,
and
then
actually
we
have
some
script
to
once.
A
You
for
generate
each
layout,
we
actually
auto,
we
posted,
we
will
do
layout
extraction
and
then
do
simulation
then,
based
on
the
metrics
ultimate
metrics,
for
example,
cmr
or
offset
etcetera
right.
So
then
we
can
kind
of
say:
hey!
You
know
this.
This
placement
is
good,
the
other
one
yeah,
not
good
right.
So
essentially
we
can
throw
out
bad
mouth
directly
early
on
during
the
design
right.
A
So
if
we
have
this
kind
of
placement
quality
prediction,
so
we
have
built
some
cn
models
for
that
and
we
also
released
this
ut
analog
cloud
data
set
with
post
layout
simulations
right
for
certain
technology
that
tsmc
that
we
used
right,
40
nanometer.
So
I
think
this
is
a
pretty
interesting
direction
in
a
sense
that
okay,
if
you
can
automatically
generate
because
for
manual
designers,
there's
no
way
that
they
can
explore
so
huge
design
space.
A
But
once
you
have
this
analog,
usually
they
were
based
on
their
like
past
experience
right,
but
now
you
can
actually
generate
tens
of
thousands
of
different
layouts
and,
let's
see
hey,
which
one
is
better
right.
So
that's
how
we
can
then
use
this
to
guide
our
placement.
B
A
A
B
A
Exactly
right
so
and
then
in
terms
of
our
analog
I
mean
the
entire
design
flow
right,
so
we
can
have
a
hierarchical
flow
and
we
can
also,
I
think
I
already
mentioned
this
hierarchical
flow,
but
we
can
also
do
simulation
in
the
loop
when
needed,
because
simulation
is
very
expensive.
You
don't
want
to
do
simulation.
A
You
know,
while
you
are
running
all
these
places
and
routes
right,
so
post
layout
extraction,
that's
very
expensive,
but
with
this
kind
of
prediction
you
can
help
you
to
do
that.
But
when
you
are
very
close
to
you
know
the
let's
say
later
stage
you
are
converging,
you
may
want
to
do
real
simulations
and
see
that
hey.
You
know,
after
you
have
done
your
present
route,
whether
that
will
really
meet
your
performance
target
right.
So
that's
why
we
were.
A
We
have
this
kind
of
options
there.
You
can
do
simulation
in
the
loop
when
needed,
especially
at
the
later
stage,
and
because
this
simulation
it
is
very
accurate
and
also
we
can
combine
it
with
a
bayer,
optimization
and
then
to
adjust.
For
example,
our
placement
routing
knobs
like
to
try
to
fine
tune
our
quality
of
results.
A
All
right,
so
I
think
I
already
talked
about
right
so
essentially,
for
example,
during
the
placement
we
can
then
adjust
the
net
weighting,
and
then
you
can
regenerate
new
placement
and
routing.
Then
you
can
do
this
loop
and
that
helps
hopefully
I
mean
our
main
reason
to
do.
This
is
like
also
hope
that
hey
you
know
it's
a
one
pass
and
it
will
be
a
pep
out
kind
of
quality.
But
you
know
if
we
just
do
some
wireless,
we
are
not
sure
whether
that's
temporal
quality
right.
A
So
at
the
end,
you
probably
want
to
have
some
of
this
in
the
flow
right.
Okay,
all
right!
So
another
thing
that
during
the
placement,
as
I
mentioned
right,
we
can
also
add
some
system
signal
flow.
For
example,
you
know
that
this
system
signal
flows
from
here
to
here
here
to
here
right.
So
if
you
have
optimized
the
system
flow,
hopefully
it
will
be
more
straight.
Otherwise
you
may
have
like
you
know
detours,
and
if
it
is
irregular,
you
know
signal
goes
north
and
then
those
south
again
right.
That's
not
good
right.
A
A
Yeah
so
as
I
mentioned
here
right,
so
we
also
once
you
have
this
kind
of
system
flow.
Our
placement
can
consider
the
system's
flow
and
we
can
extend
the
analytical
placement
engine
to
consider
this.
For
example,
you
know
we
want
to
minimize
those
kind
of
angles
right,
so
you
know
if
the
angle
is
zero.
So
that's
like
straight
right.
A
If
angle
is
very
big,
that's
not
good
right,
so
it
means
you
have
more
detour
right
so
anyway,
we
can
then
add
those
kind
of
system
signal
flow
into
our
non-linear
placement:
optimization
engine,
okay
and
now
in
terms
of
routing
right,
so
routing,
and
so
our
input
is
the
routing
constraint
and
placement
plus
the
pdks
design
rules
right
and
then
our
output
needs
to
be
rbs
and
drc
cleaned
gds2
layout,
so
but
routing
is
actually
quite
challenging.
There
are
actually
a
diverse
human
experience.
A
You
know
you
know
usually
right
so,
especially
for
analog
designs.
They
have
some.
You
know
there
are
ways
to
do
it
right
and
there's
also
many
challenges
around
ability,
ping,
assess,
etc
and
all
the
design
rules
right.
So
that's
why,
when
we
are
doing
routing,
we
have
published
some
kind
of
global
routing
for
which
we
call
genius
route,
which
provides
some
routing
guidance
again
based
on
some.
You
know,
machine
learning.
This
is
a
generative
adversary
network.
A
You
can
say
hey,
you
know
it
should
roughly
route
in
this
kind
of
you
know,
regions
this
way
stuff
like
that
right
and
then
you
can
then
use
this
to
guide
the
detail
out
right,
but
in
our
magical
1.0
right
we
actually
had
a
more
flat
route
right,
so
it's
directly
a
grid-based
routing
and
so
which
can
handle
drc,
because
our
early
version
of
the
our
early
version
of
magical
router
is
not
a
grid
based
router,
it's
more
fine
grid
or
even
gridless
routing,
but
but
that's
pretty
challenging
for
us
to
do
all
the
drc
and
especially
advance
the
technology
nodes
right.
A
So
now
we
are
having
a
group-based
routing
for
speed
and
also
the
drc
handling
and
the
core
engine
is
the
astr
search,
which
is
very
popular
in
all
the
routing
engines,
and
we
have
drc
check
and
also
the
routing
will
handle
the
symmetrical
aware
this
in
our
routing
and
our
router
also
support
the
variable
widths
and
you
also
have
multiple
rear
cuts
right
and
when
you
are
dealing
with
power
and
ground.
We
have
some
special
handling
and
wheels
have
post
processing
steps
to
fix
drc
errors
again
right.
This
is
the
overall
routing
flow.
A
You
have
some
pre-processing
and
then
you
have
some
core
routing
procedure
here
and
then
you
have
poster
refinement
to,
in
particular
correct
the
drcs.
So
in
the
core
routine,
we
have
some
pin
clustering
and
constraint
rail
connection
and
etcetera
right.
So
those
you
know,
this
is
kind
of
a
lot
of
round
and
then
some
department
reroute
process.
A
A
We
may
have
multiple
weeds
and
so
on
so
forth,
multiple
beer
cuts,
because
ultimately,
right
as
I
will
show
you
right
so
when
we
develop
a
1.0,
so
we
are
at
that
time
trying
to
tap
out
the
chip
right
and
so
as
we,
since
we
need
to
tap
on
this
chip
right,
there's
a
lot
of
like
engineering
details
and
the
dirty
stuff
we
have
to
handle
right
now,
including
like
also
ir
job
etc.
A
So
now
let
me
show
you
some
results,
and
so
we
have
tested
the
magical
on
many
different
components.
So,
for
example,
like
here
is
a
comparator,
and
this
is
the
manual
layout,
and
this
is
our
magic
layout,
as
you
can
see
these
two
layers
that
look
very
differently.
However,
if
you
do
post
extraction
simulation,
I
mean
magical
is
still
I
mean
this
is
the
early
version
of
magic
by
the
way.
A
So
I'm
not
our
the
latest
one,
but
you
know
it's
not
as
good
as
manual,
but
you
know
it's
still
pretty
reasonable,
and
but
in
terms
of
this
is
another
more
complicated
one.
It's
a
two-stage
mirror
compensated.
Ota
and
you
know,
are
my
collaborator,
my
co-pi
nanzon,
and
he
had
those
capped
out
before
this
is
a
manual
layout
which
has
been
tapped
out
in
tsmc49
meter,
and
this
is
our
magical
layout
again
right.
A
The
layout
looks
very
different,
and
but
if
you
do
post
value
extraction
in
terms
of
all
these
different,
you
know
metrics
such
as
dc
gain
and
the
fast
margin,
cmr
etc.
A
So
I
think
yeah
it's
pretty
comparable
and,
for
example,
of
course,
this
offset
at
this
time
is
still
not
as
good
and
offset
by
the
way
right,
it's
quite
related
with
the
symmetry
and
but
later
on,
our
we
have
our
newer
version
actually
is
more
powerful
right,
but
again
right.
So
here
it
shows.
You
know
the
magical
can
get
pretty
competitive
results,
but
in
terms
of
runtime
right,
if
you
do
do
this
by
hand
right,
so
it
could
take
a
week
or
so
right,
but
with
our
magical,
it
runs
in
seconds.
A
So
here
are
just
some
more
designs
right,
so
there's
a
schematic
and
the
layout
between
manual
and
magical,
and
this
is
another
inverter-based
ota,
so
we
have
tried
a
different
kind
of
circuits
right
now.
Let
me
show
you
actually
one
of
the
real
exciting
thing
that
we
had
right.
So
we
actually
you
know
for
this
magical
1.0.
A
A
So
here
is
a
schematic,
as
you
can
see,
it
has
variables
of
blocks,
including
three
integrators
and
one
passive
and
two
active
and
also
have
you
know
two
fr
fir
based
feedback,
dlcs
and
then
comparators
and
also
a
bunch
of
digital
logics,
right,
blue
logics,
and
so
this
is
the
the
entire
like
actually
packaged.
A
As
you
can
see,
here's
our
adc
core-
it
has
some
peripheral
circuits
to
do
to
help
to
do
the
testing
right
and
and
this
core
area
is
about
22
000
square
micron
and
the
chip
is
about
800
micron
by
this
entire
chip
is
800
by
550
micron,
and
so,
as
you
can
see,
we
kept
it
out
at
the
tsmc
40
nanometer
right
thanks
to
tsmc
yeah,
so
yeah.
Actually
we
have
a
shuttle
free
shuttle
at
ut
hosting
and
that's
why
we
we
can
actually
have.
A
Okay,
here
here's
the
basically
the
adc
part-
and
these
are
some
pair
fairies
and
here's
wire
bonding
and
we
have
actually
got
a
a
bunch
of
chips
back
and
so
here,
as
you
can
see,
it's
eight
different
chips
which
have
been
packaged
and
measured,
and
this
is
one
of
the
representative
chip
measurement.
So,
as
you
can
see,
the
bandwidth
is
a
5
megahertz,
and
this
one
is
a
500
kilohertz
and
the
sfdr
and
sndi
are
all
pretty
competitive
and
we
also
round
for
different
chips.
A
As
you
can
see,
the
the
they
are
actually
pretty
consistently
in
the
range
between
78
and
8182,
and
this
is
the
sndr
again
right.
It's
pretty
consistent
and
the
design
margin
is
also
actually
pretty
pretty
good,
so
we
can
also
compare
it
with
other
state-of-the-art
continuous
time
there
are
sigma,
adcs
and
so
actually
among
these
right.
So
this
actually
so
this
one
is
actually
the
previous
chip
that
has
been
tapped
out.
Basically,
our
design
is
the
same
as
this
design.
It's
just
like
this
one.
A
Our
layout
is
100
automatic
and
this
one
is
100.
This
one
is
a
manual
layout
like
it's
100
manual,
and
this
is
100
magical,
and
we
also
have.
I
mean,
of
course,
before
this
is
actually
a
pretty
high
performance
design.
It
was
published
in
iopre,
solid
state
circuit
letter,
it's
a
very
good
journal,
and-
and
so
at
that
time
it
also
compared
with
some
other.
You
know
continuous
time
that
has
actually
pretty
good
performance.
A
So
then
we
compared
the
you
know
automatic
layout
versus
this
manual
layout.
As
you
can
see.
Actually
the
over
like
floor
plan
looks
pretty
similar
right.
One
thing:
I
have
to
say
that
we
actually
the
only
thing
manual
constraint,
we
add,
is
a
sql
constraint.
We
added
the
signal
flow
and
then
the
rest
is
basically
automatic
replacement
and
routing,
and
so
and
in
terms
of
the
overall
performance
and
so
on
and
so
forth.
A
Right
as
you
can
see,
they
are
really
close
like,
as
you
can
see,
the
area
is
very
close
and
and
also
the
power
actually
for
in
terms
of
power.
Ours
is
slightly
less
the
bandwidth
and
the
frequency
they
are
all
the
same.
And
then,
if
you
look
at
the
f,
sfdr
and
sndr,
I
mean
their
sfdr
is
slightly
better,
but
our
sndr
is
better
and
in
terms
of
the
you
know
how
many
was
per
operation.
Actually
we
are
slightly
better.
A
A
So
let
me
actually
show
you
some,
you
know
demo.
Basically,
you
know
let
me
so.
Basically,
as
you
can
see,
this
is
our
fire
structure
and,
as
you
can
see,
these
are
our
top
level
kind
of
design.
It's
just
right.
It
has
a
result,
as
you
can
see,
it's
a
net
list,
it's
a
hierarchical
design
and
it
has
different.
You
know
this
is
the
spice
necklace
right
and
then
this
is
our
wrong
script
right.
A
So
basically
we'll
just
run
a
top
level
script
and
then,
if
we
run
it
right,
so
it
will
read
the
design
generate
the
you
know
or
the
building
block.
Then
we'll
do
placement
and
routing
and
general
constraints,
and
so
actually.
A
Now
it's
already
right
around,
as
you
can
see,
I'm
routing
already
as
a
as
I'm
talking
about.
So
it's
already
done
so,
and
this
is
the
final
layout.
So
the
entire
thing
takes,
I
think,
less
than
a
minute
right.
A
Okay,
sorry,
so
all
right,
let
me
conclude
so
in
this
talk
I
kind
of
show
you
magical,
which
is
the
open
source,
analog
layout,
design
tools
that
can
do
you
know
fully
automatic
analog
layout,
but
it
can
also
take
designer
inputs
if
you
give
us
the
the
constraints,
so
the
key
components,
including
device
generation
automatically,
but
in
terms
of
intellectual
part-
mostly,
you
know,
how
do
we
do
automatic
constraint
generation?
A
How
do
we
do
placement
and
then
how
do
we
do
it
around?
But
we
also
provide
you
with
a
device
generation
script
so
that
you
can
also
to
make
it
more
open
source
and
it
has
been
silicon
proven
using
a
tapout.
It's
a
actually
pretty
high
performance
adc
and
we
have
already
made
the
open
source
available
under
bsd3
license.
So
it's
permissive
license
and
we
also
have
released
besides
this
magical,
1.0
open
source
code
for
the
you
know
for
the
layout
systems.
A
So
as
long
as
you
can
afford
to
do
some
simulations,
then
we
basically
just
dump
those
into,
and
when
we
run
automatic
script
to
do,
post
out
extraction
and
simulation,
then
we
can
kind
of
do
the
level
right
once
we
label
whether
this
placement
is
good
or
not
good,
etc.
Then
we
can
actually
do
this
kind
of
you
know
we
can
then
do
learning
right.
I
I
think,
there's
definitely
a
lot
of
room
for
you
know
to
grow.
A
This
kind
of
data
sets
right
not
just
for
what
we
have,
but
you
know
to
grow
this
all
right.
So
these
are
the
magical,
related
publications,
and
so
we
started,
as
you
can
see,
ispd
2019
and
most
recently
we
have
some
cicc
and
also
a
new
black
paper
to
be
presented.
A
So
all
right
with
that,
I
would
like
to
also
thank
my
team,
so
yeah.
They
are
very
awesome
and
my
magical
team
so
including
some
three
current
phd
students
mindy
he's
in
the
audience
karen.
How
cannot
attend
now,
but
currently,
actually
they
are
interning
at
the
nvidia
right.
So
we
are
trying
to
also
extend
the
magical
to
the
future
finfet
type
of
technologies
right
and
also
my
postdoc
xiuan
he's
an
analog
designer
and
of
course,
my
co-pi
nansoon
and
so
he's
also
analog
designer.
A
To
a
really
hardcore
analog
designer
so
also
like
shaolin
is
a
former
postdoc
and
he's
not
an
assistant
professor
at
georgia,
tech
and,
and
also
two
other
like
another
postdoc
and
my
former
students,
there
have
been
heavily
involved,
so
without
them
this
is
impossible,
but
I
think
we
are
very
happy
about
what
we
have
got
so
far
and
we
want
to
push
continue,
continue
to
push
magical
towards
more
functionality
and
support
more
different
kind
of
circuits
and
also
different
technologies
right.
A
But
I
have
a
relatively
small
team,
so
you
know
we
can
only
do
what
yeah
what
what
what
we
can
be.
Realistically,
you
know
be
able
to
do
that.
Okay
with
that,
I
think
I
like
to
close
and
conclude
and
thanks
everyone
yeah
I'll,
be
more
than
happy
to
take
any
questions.
B
Thank
you
so
much
david.
Do
you
want?
Do
you
want
to
do
a
real
demo?
No,
I
see
that
professor
kong
has
a
couple
of
questions
in
the
chat.
I
don't
know
if
you
want
to
take
those
first
or.
E
F
Yeah
hello
from
silicon
labs,
professor
pan,
thank
you
for
for
your
presentation.
It
was
very
interesting,
so
I
have
a
couple
of
questions
and
they
are
mostly,
let's
say,
related
to
machine
learning,
algorithms,
that
that
you
kind
of
used.
I
can
see
that
you're
working,
like
all
the
all
the
examples
that
you
presented
behind
40
nanometer
tsmc
technology.
F
So
my
question
goes
into
direction
because
you
heavily
rely
on
ai
and
machine
learning.
You
know
what
is
basically
technology
portability.
You
know
how
much
overhead
do
you
expect?
That
is
first
question.
The
second
question
is,
let's
say:
align
and
magical
and
back
have
the
same.
F
F
So
do
you
see
that
there
is
a
way,
because
all
these
projects
are
part
of
this
initiative
that
in
the
future,
some
standardization
and
such
that
there
you
know
there
will
be
some,
let's
say,
a
convergence
point
where
these
three
frameworks,
which
are
open
source,
could
kind
of
be.
You
know
good
practices
could
be
used
from
one
framework
to
another.
A
A
Of
course,
if
you
have
a
new
technology
right,
so
probably
you
have
to
retrain
it,
but
there
are
also
techniques,
so
called
transfer
learning
right.
Actually,
my
group-
we
have
done
quite
a
bit
of
that,
for
example,
for
the
social
feel
related
right
so
to
transfer.
If
you
change
some
technology
from
the
one
technology
right,
you
can
transfer
the
bulk
of
the
model,
but
still
with
some
limited
new
learning
data,
you
can
kind
of
train
from
the
current
model
to
migrate
to
a
new
technology
right.
So
can
I.
F
F
Is
it
possible
to
use
those
data
sets
and
algorithms,
and
then
you
know,
following
your
procedure
like
to
retrain
and
do
the
transfer
for
another
technology
node,
I'm
asking
because
you
know
we
are
interested
also
to
kind
of
repeat,
learn
from
you,
but
we
need
to
know
what
are
the
possibilities
with
the
things
that
you
share.
Thank
you.
A
G
C
And
I'm
one
of
the
magical
team
members,
so
in
terms
of
answering
that
question,
if
you
have
magical
installed-
and
so
I
think,
there's
like
two
part
of
your
question
is
what
is
if
the
model
could
be
transferred
and
the
second
is
if
the
whole
framework
could
be
transferred.
So
in
terms
of
the
first
one,
I
think
it
would
be
sort
of
difficult.
So
if
like
that,
specific
model
would
be
directly
transferable
to
another
technology
without
any
retraining.
That
would
be
hard.
C
So
you
need
to
have
some
sort
of
data
to
retrain
your
model,
but
on
top
of
that,
I
think
the
framework
could
be
transferred.
So
if
you
can,
let's
say
you
have
another
technology,
probably
like
65
or
even
28,
and
you
transfer
the
entire
framework
like
magical
with
the
placement
analysis
into
that
new
framework.
You
can
entirely
just
generate
that
generated
a
whole
new
data
set
on
your
new
technology
and
that
still
would
work
right.
C
So
it's
not
dependent
on
the
technology
known
if
you
can
transfer
the
entire
framework
of
magical
to
another
technology
node.
But
again,
if
you're
you're
saying
that
I
have
something
that's
working
on
40
can
when
I
do
that
in
22.
I
still
think
that
could
be
done
with
transfer
learning,
but
it
would
be
more
difficult
than
transferring
the
entire
framework
into
another
technology
and
working
from
that.
A
Okay,
so
me
miyana,
so
this
regarding
your
question
like
other
open
source
like
analog
layout
systems,
right
back
and
align
and
magic,
correct,
so
align
and
magical.
I
think
we
have
some
similar
principle
in
the
sense
that
we
are
doing
automatically
generated
both
of
us.
Actually,
we
are.
We
are
supported
by
the
idea
program,
but
I
think
the
there
there
is
a
little
bit
difference
in
the
sense
that
the
aligned
are
more.
A
I
will
say,
therefore,
they
focus
on
more
regularity
structure
and
we
are
now.
I
think
they
are
more
in
the
finfet
type
of
technology
and
we
are
more
bulk,
and
so
we
can
do
very
fully
kind
of
unstructured
like
analog
layouts
right,
but
I
think
we
have.
We
share
some
principle
of
thinking.
In
terms
of
you
know,
how
do
we
do
automatically
mail
constraint
generation
and
then
automatic
replacement
and
routing?
So
in
that
sense
right,
so
we
do
share
some
commonity,
but
we
are,
you
know.
A
I
think
that
the
main
focus
is
like.
Currently,
we
have
been
targeting
more
about
technology,
I
mean,
for
example,
tsmc
right.
We
don't
have
a
sense
of
the
global
and
there
are
mostly
focusing
on
global
warming
like
those
fintech
technology,
but
in
terms
of
bag
right,
I
think
the
bag
is
basically
they're
building.
I
think
it's
it's
not
fully
automatic
right.
It's
like
you
have
to
write
a
software
to
generate
a
layout,
essentially
so
the
the
I
think
ultimately
right.
A
So
I
think
how
do
I
say
right
so
analog
is
such
a
challenging
problem
right,
so
people
haven't
been
but
haven't
been
able
to.
You
know
they're,
mostly
even
draw
layouts
right,
that's
terrible!
Right!
Writing
software
like
a
bag
is
already.
You
know
much
a
bigger
step
to
help
that,
but
what's
magical
and
align
is
really.
You
know
you
give
us
knowledge
now
we
just
you
know
automatically
generate
the
final
layout
right
without
you
know.
Even
writing.
A
B
I
think
one
of
the
challenges
relative
to
convergence
of
technologies
as
I've
shared
a
bit
with
tom
sparrow,
who
works
with
andrew,
but
certainly
I've,
seen
this
within
companies
as
well
and
michelle
lotus
is
on
the
call
who
I
worked
with
that
saw
in
oracle
and
synopsis
about
two
right.
Is
you
know,
from
a
perspective
of
establishing
a
framework
where
different
components
can
be
defined
with
an
api?
That's
well
governed.
That
would
enable
innovation
within
the
api
layer.
That
would
then
allow
researchers
to
contribute
to
that.
D
Yeah-
and
this
is
thomas
from
infineon,
so
first
david
thanks
for
this
great
presentation
very,
very
interesting.
I
can
also
agree
to
what
rob
use
just
said
that
I
think
this
is
a
stepwise
approach.
What
we
are
currently
trying
to
do
internally
in
our
company
is
more,
maybe
thinking
into
in
this
back
direction.
First,
because
that's
not
fully
automated
yet,
but
you
have
the
first
challenge
that
you
have
to
train
your
analog
designers,
more
programming
and
this
kind
of
stuff,
and
then
I
can
imagine
that
the
next
step
will
be.
D
Then
definitely
this
request
to
do
more
automatic
stuff,
and
then
you
also
write.
Then
probably
some
companies
will
come
and
say:
yeah.
We
need
more
automation
for
for
bulk
technologies
and
others
will
come.
We
need
more
analog
automation
for
finfets
and
then
I
think,
all
of
three
solutions
back
align,
magical
or
then
in
some
years
maybe
they're
called
in
a
different
way.
Then
we'll
have
their
the
reason
to
exist
and
even
then
to
interlink
with
each
other
and
yeah.
D
If
you
then
also
have
some
framework
here,
you
can
plug
things
in
and
out
and
so
on.
I
can
imagine
that
such
such
a
setup
with
a
lot
of
ideas
coming
from
them
from
universities,
changing
then
small
parts
of
this
bigger
framework
could
be
also
very
interesting,
then,
for
for
companies
yeah
like
ours,
but
really.
A
A
Really
really
impressive.
Thank
you
very
much,
thomas
yeah.
I
think
your
comment
is
really
well
taken
right.
I
think
that
yeah
I
mean
at
this
stage
right.
I
think
they
are
all
growing
right,
so
we're
at
a
certain
point
right.
So
we'll
we'll
see
how
to
kind
of
you
know.
The
nice
thing
is
that
they
are
all
open
source
right.
So
that's
really
nice,
so
yeah.
D
But
I
think
I
mean
if
we,
if
we
are
smart
enough
here
and
creative,
maybe
with
small
effort,
we
can
bring
them
together
and
then
it's
maybe
getting
attractive
again
for
academic
guys
as
well,
because
then
you
can
plug
and
change
only
parts
of
it.
You
don't
need
to
reinvent
the
complete
framework
here
again,
so
your
reuse
then
may
be
magical,
but
you
have
a
great
idea
at
another
university
to
change.
I
don't
know
the
router
or.
D
B
That's
good
so
david.
I
would
appreciate
the
fact
that
the
work
can
generate
different
scenario,
types
of
layouts
very
quickly
and
then
and
pick
the
best
one.
I'm
just
curious.
Has
anyone
yet
in
practice
use
this
framework
for
to
aid
designers?
If
you
will
so
you
know,
you
certainly
shared
very
good
results
that
that's
being
generated
by
magical,
but
I'm
wondering
if
folks
would
possibly
use
that
as
a
point
to
maybe
just
tune
it
slightly.
B
You
know
to
get
to
get
it
to
where
they
totally
want
it
to
be.
In
other
words,
the
automation
is
actually
is
acting
as
an
accelerator
in
the
overall
design
process.
B
I'm
just
curious
right
because
I'm
just
thinking
in
terms
of
industrial
application,
where
you
know
the
the
automation
gets
you
to,
let's
say
98
of
what
your
design
goal
is
and
then
you
you
manually,
tune
it
a
layout
designer
mainly
tunes
it
just
for
that
last
little
bit.
That's
I'm
just
curious.
If
anyone
has
tried
this
yet.
A
Well,
I
haven't
you
know,
because
this
is
you
know,
industry
people
we
made
it
open
source
and
some
you
know
we
do
have
people
talk
to
us
right
right
right,
no,
but
the
they
probably
won't
tell
us
the
details
how
much
they
have
been
using
it
or
stuff
like
that
right.
I.
A
Yeah,
that's
why
you
know,
but,
but
I
I
think,
the
things
that
you
know
we
have
made
in
open
source
and
this
framework
right,
so
anyone
can
use
it
and
it's
permissible.
So
that
means
you
know
once
they
use
it.
They
don't
have
to
tell
us.
So
that's
right.
Okay,
yeah
bye
for
the
question
yeah
yeah,
but
we
have
been
talking
to
many
different
companies
right.
B
Okay,
if
not
thank
you
david
and
team,
I
appreciate
the
presentation
day.
I
thought
it
was
excellent
work
and
the
presentation
was
very
good
as
well.
All
right.
Thanks,
rob
thanks.
Everyone.
B
Okay,
so
I
will
I
have
updated
the
notes
from
the
meeting
which
I'll
just
resend
out
to
folks
that
see
it,
and
I
do
want
to
work
on
the
agenda
for
next
time.
So
I
will
do
that.
Some
of
the
topics
I
have
here
is
like
is
creating
a
soft
road
map,
also
looking
at
an
open
source,
ip
catalog
and
then
also
talking
about
methodology
sharing
and
best
practices.
B
In
terms
of
the
next
presentation,
perhaps
we
could
have
an
update
from
berkeley
on
chip
yard
and
bag.
That
might
be
the
next
academic
presentation.
So
let
I
will
circle
back
on
that,
so
any
questions
or.
D
Comments
rob,
I
think,
the
the
comments
of
andrew.
Let's
say
these
questions
that
he
post
there
in.
D
I
think
they
are
also
available
to
that
not
to
be
forgotten,
then
maybe
you
put
them
also
into
your
list.
I
copied
them
into
the
minutes
from
the
meeting.
Yes,.
D
B
No,
no,
I
totally
agree
with
that
yeah
and
thank
you
for
calling
me
on
that.
B
Thank
you.
So
let
me
I
will
I'll
summarize
these
and
then
we
can
formulate
next
steps
for
the
meeting
and
do
that
online
until
we
set
up
the
meeting,
which
I
hope
to
do
in
another
in
two
weeks,.