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From YouTube: Lowering Barriers to chip design
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B
B
Yeah
thanks
thanks
Rob
for
the
presentation
introduction,
so
today,
I
will
be
talking
about
Lauren
berries,
to
chip
design
using
open
fa
stock,
as
well
as
the
activities
we
do
at
the
adult
working
group
with
Rob
Mains
here.
B
So
first
of
all,
I'll
go
a
little
bit
and
give
an
introduction
of
who
we
are
here
this
our
project
started
with
fa
stock,
which
is
a
DARPA
program.
It
started
four
years
ago
or
five
years
ago.
It
was
a
military,
University
and
Industry
effort.
B
So
I
gave
a
couple
talks
at
chips,
Alliance,
there's
a
couple
of
stuff
that
you
can
go
and
check
there,
basically,
the
framework
and
how
it
works.
I
don't
want
to
go
too
much
into
details.
I
would
like
to
focus
on
what
we've
done
this
year,
the
tape
outs
and
some
of
the
updates
on
the
methodology
and
the
on
the
flow.
B
So
these
are
a
couple
checkouts.
You
have
done
over
the
course
of
the
program.
These
are
mainly
using
close
tools
but
also
open
source
tools.
So
we
started
with
the
tsmc
65lp
design.
We
checked
it
out
and
demonstrated
at
Salt,
Lake,
City,
I
think
two
years
now
or
two
years
now,
and
then
we
did
a
couple
tape
Us
in
the
F12.
We
included
more
generators.
B
B
So
those
are
a
couple
screenshots
of
our
takeouts
and
I'll
go
into
more
details
as
we
go
so
now,
after
the
program
from
DARPA
added,
we
we
we,
we
don't
have
the
funding
so
Google
was
was
one
of
our
benefit
manufacturers
and
nist
as
well.
We
went
to
the
umbrella
of
chips
Alliance
in
the
Linux
Foundation.
B
We
collaborate
a
lot
with
the
open
road
and
we
started
using
tools
like
GDs
Factory
and
align
and
there's
a
couple
updates
on
internet
on
YouTube
on
the
stocks
here
through
through
chips
Alliance.
So
please
go
there,
but
my
group
is
a
small
group.
We
have
five
students
and
a
postdoc
and
we're
working
on
couple
generators
still
and
a
couple
tape
outs.
B
I'll
just
go
briefly
just
to
remind
people
here
what
is
open
to
Facebook,
so
openfa
stock
addresses
automated
Dynamic
design
right
and
here
I
made
it
a
really
small
workflow
diagram
on
on
the
left
of
what
would
be
a
traditional
analog
layout
flow
today
and,
as
you
all
know,
most
of
it
is
custom
and
require
multiple
iterations
from
schematic
entry
to
layout,
then
simulation
and
so
forth,
while
the
digital
flow
or
the
grid
based
flow
is
highly
automated
for
a
while
now,
so
the
idea
is
basically
to
take
what
would
otherwise
be
a
full
custom
layout
and
shoehorn
it
into
it.
B
The
cell,
based
digital,
automated
design
flow,
a
methodology
which
is
pretty
amenable
here
to
the
available
logic,
synthesis
and
placed
on
Route
tools,
either
be
it
proprietary
or
open
source
tools.
So
this
is.
This
is
the
whole
framework.
This
is
a
couple
of
Legacy
design
from
isscc,
vlsi
and
cicc.
There's
much
more
of
these
blocks
here.
I
I
couldn't
fit
them
all,
but
there's
much
more
that
you
have
created,
especially
on
the
open
source
side.
These
are
the
auxiliary
cells.
B
So
basically
we
try
to
identify
analog
functions
in
these
blocks
or
circuit,
which
are
highlighted
in
blue,
and
we
try
to
split
them
in
small
blocks
or
auxiliary
cells,
so
that
we
can,
you
know,
create
standard
cell
and
show
horn
them
in
the
digital
flow.
So
you
can
have
a
lot
of
variants
of
these
everybody
cells.
They
are
usually
12
transistors
below
and
it's
very.
They
are
very
easy
to
modify
to
create
multiple
variants
of
your
design.
B
We
also
added
some
some
supportive
align
Tool,
it's
a
little
hard
when
you
use
a
vague,
a
layout
generator
these
days,
but
basically
we
try
to
add
some
constraint
to
a
line
to
create
our
auxiliary
cell,
so
that
makes
it
the
last
piece
of
automation
of
openfa
stock.
B
So
here
so
this
is
the
the
tool
chain
we
we've
been
using
in
the
dark
part
program.
It's
called
fa
solve
it's
based
on
proprietary
tools,
it's
using
synopsis,
Cadence
and
all
the
closed
tools.
But
my
focus
here
is
about
open
a
face
Arc,
and
we
two
years
ago
we
started
the
flow
based
on
the
existing
open
source
tools.
Yours
is
we
started
using.
Sometimes
you
should
sure
login
usdm,
thanks
to
send
micro
and
Google,
open
road,
magic
nature
and
Kelly
out
and
just
python
size.
B
So
that's
the
whole
two
chain
we
are
using,
but
you
can
see
it
on
my
last
update
in
the
chips
Island
stick
update.
We
started
using
much
much
more
stuff
in
there
we
started
using
much
more
customized
layout
and
we
started
using
something
called
GDs
Factory
which,
which
is
supported
here
in
Google
by
yourkin,
who
is
a
Protonix
guy.
So
we
thought
that
to
to
a
tape
out,
we've
done
with
ness
was
very.
It
was
perfect
actually
for
for
what
we
wanted
to
do
for
test
structures.
B
So
we
started
making
this
python
apis
that
basically
create
polygons
that
you
know
create
for
you,
test
structures
that
are
useful
for
your
design.
So
I'll
go
in
more
more
details,
but
that
basically
evolved
our
flow
into
more
than
basically
just
using
a
cell
based
approach,
but
using
also
customized
layout,
which
is
really
required
for
some
of
the
adult
blocks.
If,
if
you
were
the,
if
you're
used
to
analog
design
so
anyway,
so
I'll
move
now
to
the
tape
outs,
these
are
all
k-pops.
B
These
are
two
years
ago
mpw1
we
made
a
a
sensor
array.
We
made
64
of
them
using
the
skywater
technology.
We
included
an
ldo
that
we've
never
been
able
to
test,
but
we
are
the
time
sensor
are
working
and
we
published
the
work
in
the
solid
state
circuit,
Community
or
solid
state
circuit
letters
which
is
pretty
good
because
it's
state
of
the
art
and
shows
really
good
results.
B
So
I'll
I'll
go
into
more
details
here
to
make
the
temp
sensor,
we
had
to
create
some
functions
or
functionalities
in
openload
like
voltage
domains
as
you
can
see
on
the
right
and
non-default
reality,
and
so
these
are
very
useful
in
Outlook
design,
but
they
can
be
also
very
useful
to
anyone
who's
doing
custom
design.
So
actually,
in
our
repo
I
mean
there
is
100
star,
but
there's
a
lot
of
people
that
are
using
our
scripts
to
to
to
do
their
custom
layouts,
which
is
really
good.
B
So
these
are
the
measured
results.
These
are
not
simulations.
We
we
were
among
the
first
to
have
second
working
in
this
technology.
B
This
is
the
good
thing
about
generating
64
sensors
is
that
you
can
map
the
design
space
exploration
for
temp
sensor.
There's
a
couple
metrics
that
are
interesting
here.
There's
the
inaccuracy
resolution
time
conversion
power.
So
here
you
can
just
decide
which
sensor
you
want,
and
this
map
is
probably
changed
over
these
past
two
years,
because
we've
been
updating
our
tools
and
and
Flow.
B
We
also
used
multiple
flavors
in
this
technology,
so
there's
an
HD
transistor,
high
density
start
as
a
library
and
the
high
speed
one.
So
it
gives
you
different
Footprints
in
in
your
chip
and
that
can
be
useful
depending
on
what
inaccuracy
or
how
much
area
you
have
right.
B
These
are
more
results.
We
actually
tested
the
64
sensor,
so
we
made
the
Python
scripts
and
they
are
all
on
GitHub.
The
chips
are
available.
If
anyone
want
to
test
them,
but
we
generated
all
this
data
here,
I
measured
data
and
we
have
a
below
one
degree-
C
inaccuracy,
which
is
state
of
the
art
and
you
can
go
in
the
data-
is
available
on
GitHub.
You
can
go
and
dig
in
and
see
what
is
interesting
to
you.
This
is
a
comparison
table.
B
We
we
do
research,
so
we
have
to
compare
to
other
people.
We
compared
to
jss,
CC,
say
ICC
and
ICC
papers,
which
is
really
great.
One
thing
that
I'll
highlight
here
is
the
conversion.
Time
is
really
it's
a
decent
compared
to
others,
but
it's
horrible
for
our
previous
sensor.
B
So
we
improved
that,
but
one
of
the
sensors
is
really
good
so
anyway,
having
been
able
to
generate
multiple
of
these
sensors
allows
you
to
get
different
trade-offs
and
that
that
can
be
very
important
to
designer,
especially
if
you're
doing
an
SOC
or
any
system
all
right.
So
this
is
another
tape
out.
You
still
didn't
get
the
Silicon
back,
hopefully,
you'll
get
it
soon
from
e-fabulous,
but
this
is
mpw2.
We
did
the
same
thing,
but
now
with
a
digital
ldo,
we
did
10
10
of
them.
B
We
simulated
them
and
everything
made
sure
everything's
fine.
We
created
some
debugging
because
you
can't
just
put
an
ldo
and
hope
that
it's
going
to
work
right.
So
we
had
to
do
some
anode
buffers
voltage
references.
We
also
included
an
open,
Titan
SOC
there
as
a
demonstrator
and
included
for
the
best
temp
sensor.
We
have
and
we're
taught
we
we're
good.
We
also
developed
the
flow
for
Eco
that
basically
fixes
whole
violation,
so
we're
hoping
this
Chip
is
going
to
work
and
yeah.
We
updated
our
digital
ldo.
B
We
embedded
voltage
references,
Decap,
generator
and
voltage
reference
circuits,
I.
Think
that's
what
I
wanted
to
say
there.
This
is.
This
is
just
a
zoom
in
into
the
the
Leo.
As
you
can
see
the
we
try
to
constraint
our
design
if
you're
not
familiar
how
to
we
do
that.
You
can
listen
to
our
or
go
check
our
other
talks,
but
basically
we
try
to
use
python-based
constraints
or
some
which,
since
this
is
open
source
tools,
we
create
some
functionalities
that
allow
us
to
do
a
better
layout
right.
B
So,
basically,
here
you
can
see
that
the
arrays,
the
power
switch
array
here
on
the
bottom,
is
actually
structured
in
a
manner
that
allows
you
to
have
less
variation
right
and
then
we
make
sure
the
powers
power
mesh
is
actually
built
in
a
way.
Resistivity
is
really
low
and
there's
no
now
routing
or
single
vehicles.
We
also
included
a
highly
trimmable
voltage
reference.
It's
based
on
a
duty
voltage
reference.
B
We
do
in
Michigan,
it's
actually
a
little
more
than
that,
but
it's
it's
over
here,
but
basically
that
allows
us
to
to
calibrate
for
variation
or
basically,
models,
not
being
good.
You
know
there's
different
issues
that
we're
trying
to
anticipate
here
yeah.
So
this
is
another
there's
a
couple
things
here.
This
is
the
top
diagram.
We
are
using
multiple
switches,
so
there's
10,
10
ldos
you're
asking.
Why
do
you
need
10
alleles?
Well,
we
wanted
to
address
different
clothes.
B
First
of
all,
but
we
also
wanted
to
try
different
circuit
techniques
right,
so
we
used
this
Discoverer
has
a
native
transistor.
So
that's
great.
We
use
that.
We
use
the
pmos
as
well
different
sizes.
We
use
the
standard
cell
based
comparator,
but
we
use
the
stronger
arm.
Latch
comparator
as
well,
so
I
think
that's
very
useful
because
you
can
generate
thousands
or
hundred
thousands
of
these
ldos.
B
We
just
related
then,
but
you
could
do
that
and
simulate
them
without
taping
them
out
and
see
which
one
is
great,
so
I
think
that's
very
useful
all
right.
So
this
is
the
top
diagram.
We
I
think
we
were
the
first
one
who
made
an
AMS
or
an
organic
signal
SOC.
Hopefully
it's
gonna
work
I'm
not
going
to
go
into
details
into
the
Eco
flow,
but
we
can
discuss
it
if
you
want
to
hear
more
about
it,
but
the
idea
of
this
Eco
flow
is
actually
to
improve
the
power.
B
Initially
we
tried
we
used
it
for
to
fix,
hold
violation,
but
that's
not
the
only
goal
we
we
are
targeting
Energy
Efficiency
and
we
want
to
reduce
leakage
in
a
couple
other
things.
So
this
Eco
flow
is
very
useful
for
this
type
of
things
right,
so
the
other
tables
we
made
are
two
then
for
the
nist,
Nano
fabrication
accelerator
and
that's
initiative,
Under
the
Umbrella
of
Google,
and
this
we
work
with
a
couple
of
other
faculties
from
Brown
and
gwu,
which
is
really
great.
B
We
have
a
weekly
meeting
if
anyone
is
interested,
we
can
I
can
invite
him
to
that
meeting.
But
the
idea
this
was
to
make
test
structures
for
cryogenic
modeling.
We,
if
you're
familiar
with
that
here.
B
Basically,
you
have
to
interface
with
the
quantum
processor
and
interfacing
with
it
at
200k
is
not
is
not
great
right,
so
you
want
to
be
able
to
run
your
circuit
at
a
lower
temperature,
which
is
one
to
four
kilograms
so
and
before
doing
that,
you
have
to
generate
building
blocks
for
that,
so
openfa
stock
sounds
like
a
good
way
to
do
that.
B
But,
first
of
all,
we
need
to
create
these
structures
to
do
this
thing,
so
we
so
we
worked
with
this
on
on
this
part
with
Brian
Hoskin,
who
is
the
PM
of
this
program,
and
we
taped
out
this
chip
here
around
first
quarter
of
2022
with
one
of
my
students
and
we
I'll
I'll
try
to
go
into
yeah
I'll
just
review
some
of
the
test
structures
here.
This
must
have
arrays.
B
These
are
very
simple
structures
line
resistance,
VR
resistance,
Precision
resistance,
so
these
are
really
simple
structures,
but
I
wanted
to
automate
them
right
and
open
a
face
off.
Is
a
cell
based
approach?
So
how
do
you
do
that?
So
that's
where
GDs
Factory
popped
in
and
we
started
using
python-based
apis
to
create
these
layouts
here
and
then
that's
where
we
discovered.
This
could
be
very
useful
to
our
other
generators
like
a
pmu
which
has
a
lot
of
fine
caps
switches
power
switches.
B
You
know
that
that's
very
useful
for
adcs
as
well
Dax,
so
I
think
this
is
awesome,
because
you
can
also
integrate
some
of
these
customized
blocks
with
a
cell
based
approach.
And
then
you
have
a
dimension
return
rule
here.
Where
you
can
you
know
you
don't
spend
a
lot
of
time
on
the
part
that
doesn't
require
attention,
but
then
you,
you
spend
some
time
on
writing
some
Python
scripts
for
some
of
the
blocks
that
require
attention
like
a
dco
for
a
PLL
flying
caps.
You
know
so
anyway.
B
The
other
blocks
we
made
is
this
ring
oscillator
here
it's
an
interleaved
placement,
as
you
can
see
on
the
left.
This
is
very
useful
for
process
entering
this
is
using
python
based
manipulation
of
the
the
dev
so
we're
hoping
in
open
world.
We
can
have
a
better
interface
to
it.
B
There's
a
couple
of
people
working
on
vsir,
IR
or
other
tools
that
could
potentially
do
this
work
here,
where
you
don't
have
to
deal
with
different
formats
like
Dev
videos
right
so
but
anyway,
this
was
one
of
the
blocks
we
did
with
the
open
road,
the
other
blocks
we
made
24
sensors
of
them.
This
is
using
openfa
socks
flow
sales
based
approach.
We
also
included
the
OSU
standard
cell
libraries
from
gym
science
group
at
OSU.
B
This
is
a
couple
other
layouts,
but
the
idea
there,
if
you
can
see,
there's
a
couple
mesh
there
and
I'll
just
zoom
in
here.
This
is
an
example
of
a
routine
or
API.
We
created
in
GDs
Factory,
where
it
takes
in
Dimensions
pitch
layers
and
just
create
a
great
mesh
for
you.
This
is
very
useful.
B
There's
a
lot
of
functions
being
used
here
to
create
smash.
There's
not
only
the
mean
cap
mesh,
these
diodes
there's
mom
cap
mesh,
there's
moscap
mesh,
so
there's
a
lot
of
them
and
you
can
reuse
that
for
for
using
this
same
function
and
then
we
integrated
everything
using
pair
dies.
These
are
bear
dies
that
are
probed,
so
they
are
very
useful.
Sorry,
but
basically
the
idea
here
is
that
we
were
able
to
reuse
this
function
here
in
our
other
generators
and
that's
how
we
added
more
customization
in
our
automated
analog
design.
B
This
is
a
resultant
test.
I
was
really
impressive,
because
this
was
done
in
two
months.
This
would
require
a
year
or
maybe
six
months
in
the
company,
so
this
is
really
awesome
to
show,
but
the
the
other
interesting
thing
is,
we
didn't
only
do
mpw5
this
year.
We
did
mpw
five
six
and
seven,
and
this
is
every
three
months
so
and
we
are
actually
loading.
We
are
basically
working
on
fpw8
we're
using
actually
much
more
complex
structures.
B
So
you
can
see
these
are
very,
very
simple
structures,
as
you
can
see
here,
we
included
the
pmu.
B
We
run
structures
that
was
done
by
gwu,
it's
on
the
right
there,
but
the
pmu
is
where
we
use
those
routines
for
measure
ways.
Sorry
flying
caps,
arrays
and
power
switches,
arrays
and
the
last
one
had
inductors
that
you
can
see
there.
Vcos
and
tias.
C
B
It's
getting
a
lot
more
complex
and
we
still
can
tape
out
in
three
months,
but
I
think
that's
by
itself
a
data
point
where
you
can
see
that
this
framework
is
working
right
in
mpw8
we're
working
on
Quantum
current
standard,
which
is
a
very
complic,
complex
circuit,
and
this
Quantum
current
standard
is
trying
to
detect
signal
defects
in
a
transistor.
So
we
have
to
create.
We
have
to
generate
stats,
so
the
idea
here
is:
we
are
trying
to
generate
as
many
as
possible
with
different
us
transition
sizes
and
different.
B
You
know
blocks
in
it.
So
I
think
it's
the
you
know
that
could
be
a
very
high
impact
project
if
you
can
get
it
to
work
all
right.
So
this
is
this
was
about
this
project.
Meanwhile,
we
did
another
takeout
in
mpw,
zero
for
GF
180,
and
that
was
done
in
less
than
a
month.
B
So
what
we
have
done.
There
is
very
simple
structures
where
we
wanted
to
make
sure
discover
this
pdk.
We
have
never
used
it,
but
one
of
them
is
a
filter,
GMC
filter,
it's
all
synthesized
the
synthesizing
oscillator,
so
we
use
the
ring
oscillators.
We
did
in
skywater
130,
which
is
just
the
same
code.
So
that's
why
we
were
able
to
do
it
in
less
than
a
month
right.
So
there's
a
lot
of
views
here.
B
We
also
made
an
array
for
non-volatile
memory,
so
we're
trying
to
see
how
it's
going
to
work.
You
know
that's
just
the
structures
here,
but
I
think
it's
going
to
be
useful
for
the
next
day
part.
So
if
you
want
to
build
a
non-volatile
memory,
all
right,
so
the
other
exciting
projects
we
did
is
our
Infinity
fat
and
we
are
using
open
source
tools
here.
So
some
people
don't
believe
that,
but
that's
possible
and
we
have
done
atgf12
a
while
back.
B
So
we
we
taped
that
on
opentite
and
SLC
same
as
the
one
we
did
in
Skyward
130
but
including
sensors,
and
are
using
open
road
as
the
main
open
source
tools.
So
there's
nothing
else
other
than
open
road.
Here
synthesis
are
using
commercial
tools
and
verification,
so
we
were
able
to
take
out
a
250
megahertz,
which
is
really
great.
Simulation
is
working
fine.
We
have
the
chips.
B
We
are
still
debugging,
let's
see
what
what
is
happening
with
them,
but
we
know
the
way
the
functional
verification
is
working
and
also
we,
but
you
know,
we'll
see,
what's
happening
with
this
chip.
The
other
tape
out
you
did
recently
last
November,
while
doing
the
other
takeouts
is
the
Intel
16
one?
It's
it's.
It's
a
it's
another
open,
Titan,
SOC
version
which
we
built
from
scratch
this
time,
because
we
want
to
make
sure
everything
is,
is
right.
B
This
is
this:
is
some
a
couple
of
diagrams
or
screenshots
here
the
the
green
stuff
is
the
buffer.
So
we,
these
staples,
help
us
push
a
little
bit
the
limit
right
and
the
limit
here
as
a
group
who
works
on
low
power
design
is
achieved.
Energy
Efficiency,
so
these
are
besides,
are
inserted
buffers
and
we're
trying
to
see
why
there's
so
many
right,
like
we're
not
doing
a
new
threshold
operation.
B
So
these
are
a
couple
things
that,
through
this
tape
out,
we
can
discover
a
lot
of
issues
that
can
push
the
limit
forward
for
open
source
tools
and
we're
able
to
tape
out
in
64
with
a
64
utilization.
But
you
had
to
roll
back
to
29
because
in
Opera
there
is
no
support
of
multi-hate
sales
for
the
tap
cells,
which
is
a
very
specific
things
in
this
Intel
technology,
and
we
weren't
aware
of
it.
B
So
we
could
have
anticipated
that
a
little
more,
but
you
know
we
still
were
able
to
do
this
and
actually
make
sure
everything
is
working
here
in
this
tape
out,
so
we're
running
at
28
megahertz,
which
is
much
more
slower
and
the
than
the
gf12
one.
But
that's
because
we
just
want
to
make
sure
everything
is
working
using
our
framework
here.
B
These
are
power
number.
This
rolls
back
to
my
point
there
about
Eco
flow.
If
you
see
the
worst
case
corner
here,
we
have
a
high
leakage
we
want
to
operate
at.
We
want
to
achieve
Energy,
Efficiency
right.
B
You
know
we're
trying
to
discover
or
trying
to
figure
out
how
we
can
improve
that
by.
You
know
the
way
we
insert
buffers
so
leakage.
There
means
that
there's
a
lot
of
buffers
sitting
around
and
just
like,
consuming
leakage
right.
So
these
are
issues
that
we
could
we
I
mean
this
is
the
teapot
was
done
like
two
weeks
ago,
so
this
is
still
fresh.
We're
still
doing
a
postmortem
massage
trying
to
figure
out
what
what
are
the
issues
and
everything.
B
The
other
cool
thing
here
is
the
temp
sensor.
So
we
we
made
another
variant
of
the
time
sensor.
The
temp
sensor
is
based
on
the
native
transistors.
It's
leakage
based
it's
running
a
sub
threshold
and
FIFA
technology
doesn't
have
a
native
transistor,
so
we
have
to
figure
out
how
to
make
it
so
anyway.
First
thing
we
use
open
source
tools
from
RTL
to
GDs
and
we
were
able
to
generate
these
array
of
sensors.
B
Each
of
them
is
different,
so
I'll
go
in
details
here,
so
there's
a
variant,
a
which
is
using
a
vgs
equal
to
zero
here,
which
is
equivalent
to
having
a
native
transistor.
If
you,
you
can
check
the
the
numbers
we
have
a
0.13
inaccuracy,
which
is
really
awesome.
This
is
specs
results
using
commercial
tools,
of
course,
but
you
know
well,
we
have
completed.
This
is
working.
The
integers
per
cycle
is
the
low
Nano
joules
per
conversion.
Zero
is
0.1
milliseconds,
so
this
is
really
awesome.
B
Man,
those
are
those
are
the
corners
or
worst
case
Corners.
We
have
so
it's
still
really
decent
result.
This
was
done.
This
is
a
two-month
tape
out
with
two
students:
okay,
the
other
variant.
Is
we,
the
virtual
vdd
inside
the
temp
sensor,
has
a
very
low
voltage
and
that
can
be
prone
to
variability,
so
we're
trying
to
get
that
vvdd
to
a
higher
voltage
and
make
sure
it
is
going
to
be
functional.
So
that's
that
that
doesn't
require
a
lot
of
work
for
me.
B
Basically
only
changing
the
cell
here,
which
is
two
transistors,
that's
very
easy
to
do
and
you
can
generate
mixable
variants.
You
can
see
the
inaccuracy
is
bad,
but
this
is
the
reason:
is
it's
not
bad?
It's
just
below
one
degree
C,
but
it's
worse
than
the
other
one.
But
the
reason
is
I
want
to
make
sure
it's
working.
B
The
other
structure
here
is
actually
a
diode
with
an
animals
and
basically
this
for
the
same
idea.
We
want
to
see
how
it's
going
to
work
in
Corners
and
you
can
see
that
the
typical
is
0.35
degrees
C
in
accuracy,
but
it's
getting
better
at
RSS
right
and
our
silicon
is
probably
going
to
behave
differently.
So
that
gives
you
a
different,
a
good
idea
of
the
silicon
and
how
it
operates
all
right.
B
So
I'm
done
now
with
the
the
tape
out
part
I'll
I'll
talk
a
little
bit
about
what
we
are
doing
in
chips
Alliance
and
our
working
group.
There's
a
technology
design
loop,
we're
trying
to
to
Define
here
with
Rob
and
there's
multiple
other
people
from
the
community
that
are
very
excited
actually
to
talk
about
these
things.
So
that
was
a
really
cool
thing
to
see
the
past
months
here
in
our
Arnold
working
group.
But
one
thing
before:
jumping
there
I
want
to
give
you
an
example
of
issues.
B
We
can
see
right,
we
can
get
silicon
working
right
and
we
can
design
things
but
energy
space
when
I
simulated.
The
time
sensor
I
showed
you
earlier
in
scour
130,
and
this
was
telling
me
hey.
You
have
a
3D
inaccurac
Y
at
-40
or
minus
20..
That
I
didn't
believe
that
I
knew
it
did
something
wrong.
When
I
used
the
closed
tools,
there
was
0.4.
So
that's
basically
eight
eight
times
the
difference
and
that's
just
inaccuracy,
that's
a
calculated
number
or
figure
of
minute.
There's
different
numbers.
There's
power
right,
that's
500
difference!
B
That's
totally
out
right!
Then
what
you
are
supposed
to
design
so
that's
very
problematic
for
High,
Precision,
analog
design
or
RF
right,
like
who's
going
to
design
who's,
going
to
be
able
to
shoot
for
design
without
having
a
good
model.
So
our
analog
cream
group
is
actually
trying
to
define
a
way
of
improving
those
models,
and
you
know
Google
has
helped
a
lot
through
team,
Ansel
and
other
other
people
here,
like
in
nist
and
cool
cat,
helped
us
to
try
and
see
what
can
be
done.
B
So
what
we
ended
up
doing
is
we're
working
with
epfa
right
now
to
test
some
of
these
structures.
They
are
already
generated
some
primarily
preliminary
measurement
results
and
they
are
actually
I
generated,
a
primary
model
based
on
the
sekv
extraction
model.
B
So
these
are
measured
results
and
that's
the
model,
but
these
are
sure
these
are
very
high,
Precision
models
that
can
be
used,
and
this
is
just
the
initial
work
that
we
started
to
do
here,
so
we're
trying
to
define
a
roadmap
here,
there's
a
lot
of
opinions
in
modeling
how
to
do
it
and
how
to
do
measurements.
B
We
don't
know
that's
a
science
by
itself,
so
it's
really
hard
to
do
that,
so
we're
trying
to
do
to
take
decisions
in
a
collegial
way-
maybe
maybe
it's
it's
gonna
take
some
time,
but
I
think
we
can
propose
or
to
define
a
set
of
standard
measurements
that
can
then
be
performed
on
the
target
Technologies
which
are
open
source
here,
so
basically
Skyward,
130,
gf1,
180
and
any
other
pdk
we
have.
B
We
can
then
use
these
measurements
to
check
the
models
provided
by
The
Foundry
and
the
and
their
pdks
using
the
dedicated
benchmarks.
We
can
extract
these
models
like
sekv
or
any
other
model,
to
have
the
designers,
design,
analog
and
RF
circuits
in
Target
Technologies,
and
we
can
Define
or
have
standard
measurements
and
the
modeling
modern
compartment
is.
We
can
have
them
and
release
them
on
GitHub,
so
everyone
can
check
them
and
provide
feedback.
B
Of
course,
I
am
everything
needs
to
be
automated,
because
we
want
this.
This
feedback
loop
here
should
be
as
automated
as
possible.
So
then,
when
we
move
from
one
open
source
pdk
to
another,
we
don't
have
to
do
this.
Work
right
and
I.
Think
openfa
stock
can
help
a
lot
here,
all
right.
So
talking
about
automation,
a
lot
of
automation
is
required
here
right,
and
that
means
that
we
need
a
lot
of
continuous
checks
to
to
make
sure
everything
is
fine.
So
openfa
stock
generates
a
lot
of
designs.
B
The
tools
are
organic,
they
evolve.
We
know
we
want
to
make
sure
everything
is
working.
We
have
the
instances
where
open
road
made
portions
picks
our
generator.
So
we
try
to
make
sure
everything
is
working
still
working,
even
though
everything
is
evolving
right
in
a
positive
way.
So
the
idea
there
is
to
create
the
CI
here
that
basically
runs
these
thousands
of
ips
that
you
can
generate
and
make
sure
they
are
not
breaking
or
regressing.
B
So
one
cool
thing
that
Google
is
doing
is
the
Google
summer
of
code,
and
we
I
got
a
couple
students
through
chips
Alliance
and
they
they
have
been
working
with
me
over
the
summer
and
we
try
to
Define
these
metrics
here
and
design
space
exploration.
So
we
we,
we
were
inspired
a
little
bit
by
Andrew
Kang
on
opennode
metrics,
so
we're
trying
to
do
the
same
thing
here
for
ammo
design
and
Define
these
metrics,
which
are
actually
even
even
more
complicated
than
digital
design.
So
I
think
this
is.
B
This
is
something
I'm
looking
forward
and
Psy
is
working
with
me
on
this
and
he's
very
he's
very
excellent
at
this
stuff.
Here
you
know
the
beauty
of,
or
the
curse
actually
of
analog
design
is
that
the
figures
of
merits
of
a
single
generation
can
be
overwhelming
right,
there's
nothing.
It
differs
from
an
ADC
to
a
temp
sensor
to
dc-dc
converter,
so
you
have
to
to
create
test
benches
for
all
of
these
and
we
do
that
in
our
generators
to
make
sure
they
are
working.
B
So
we
can
reuse
that
as
checks
in
a
standardized
Manner
and
make
sure
any
changes
in
our
test
case
are
a
circuit
in
the
tool
chain.
Doesn't
you
know,
break
our
our
our
design
so
that
this
is
basically
a
very
a
very
simplified
way
to
do
it,
but
I
think
it
it's
it's
a
really
useful
way
for
our
open
Facebook
framework.
Well,
we
plan
to
use
this
same
approach
for
the
technology,
design,
Loop
and
modeling,
which
require
to
improve
models.
B
So
basically
we
create
the
structures,
but
we
want
to
make
sure
in
our
CI
when
we
do
measurements,
We
compare
different
tools.
We
have
Zeiss
and
and
gng
spice.
We
get
different
results
from
these
tools,
which
one
is
closer
to
Silicon
results
right.
So
these
are
very
important
questions
and
we
need
to
get
an
answer
to
that
and
open
source.
Is
you
know
the
open
source,
Community
or
initiative
actually
helps
us
Define
these
things
and
move
forward?
B
The
other
thing
we
did
is
two
chipsy
lines,
but
also
with
a
lot
of
help
from
Google
and
key
people
in
chips.
Alliance,
we
were
able
to
create
this
notebook.
Competition
called
coded
chip,
so
that
was
done
with
Professor
voice
merman.
This
is
a
new
competition
through
the,
and
this
is
the
first
time
to
the
best
of
my
knowledge
that
we
have
something
in
the
solid
state
circuit
society
which
encourages
reuse,
represent
reproducibility
of
results
and
open
source
chip,
designing
software
style.
B
So
we've
run
this
this
competition
in
the
past
two
months
we
had
20
submissions,
most
of
them
are
were
great.
These
are
the
results.
These
are
the
three
first
winners
will
be
able
at
issacc,
which
is
the
flagship
conference
to
present
the
result,
show
us
their
notebook
and
and
they'll
get
a
travel
Grant
thanks
to
Google
and
chips
Alliance
all
right.
So
that
was
my
talk.
Thank
you
guys
and
please,
let
me
know
if
you
have
any
questions.
C
Thank
you
Maddie,
so
much
for
an
excellent
chat,
any
questions
from
either
here
in
present,
or
we
have
one
here
in
the
audience.
A
Can
you
talk
about
your
measurement
capabilities
to
analyze,
somebody
actual
silicon
chips
back
so
quickly,
you're
doing
lots
of
mpw?
What
sort
of
labs
do
you
have.
A
B
Oh
so
I
mean
we
do
our
group
in
Michigan
do
a
lot
of
chips.
We've
never
done
as
many.
This
is
too
many
trips
per
year
to
test
right
so,
but
we
did
a
lot
we're
doing
a
lot
of
trips
and
we
test
them
continuously
right.
So
we
have
the
student
to
do
that
and
the
test
equipment.
One
thing
we
want
to
try
to
encourage
actually
is
reproducibility
of
results,
and
actually
we
try
to
send
our
chips
to
different
people.
B
So
Nest
got
interested
by
our
dc-dc
converter
in
gf12,
so
they
are
testing
it,
but
I
have
a
lot
of
temp
sensor
and
if
anyone
in
the
room
wants
to
test
it
just
to
make
sure
everything's
working,
please
do
that,
but
I've
sent
it
to
a
lot
of
people.
A
lot
of
them
try
to
do
to
test
them,
but
it's
it
takes
some
effort
to
test
the
temp
sensor
right.
So
it's
from
-20
to
120
degrees.
C
C
B
Yeah,
so
these
generators
that
we
spend
a
lot
of
time
on
them
and
it
takes
us
a
month
like
the
Intel
16-1
temp
sensor-
was
very,
very
smooth,
but
it
didn't
it
was.
It
wasn't
like
that,
the
first
time
we
did
in
gf12
and
Skyward
130
each
time
it
took
us
longer,
but
as
we
went
it
become
really
easy.
The
bmu
is
a
famous
it's
much
more
complicated
block
because
it
requires
GDs
Factory
with
open
road
integration
so
that
that's
not
a
the
problem
is
having
the
integration
of
these
tools
all
together.