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From YouTube: Eclipse OMR Code Generator Components
Description
A brief, informal description of the major components that make up a Code Generator.
A
We
talked
as
well
about
the
extensible
class
mechanism
that
we
use
to
to
architect
the
structure
of
a
lot
of
the
classes
within
within
the
compiler
technology
and,
as
you
know,
we're
looking
at
implementing
a
64-bit
code.
Generator
I
think
that
what
I
wanted
to
do
is
to
go
through
some
of
the
various
aspects
of
the
code
generator
technology
and
make
sure
that
everyone
is
sort
of
aware
of
what
their
purposes
and
and
the
kinds
of
changes
that
we
would
need
to.
A
We
need
to
make
in
order
to
implement
a
64-bit
code
generator,
so
what
I
would
I
so
there's
about
thirteen
or
fourteen
sort
of
concepts
that
I
that
I
wanted
to
go
through.
These
are
by
no
means
an
exhaustive
list
of
all
the
things
we
have
to
go
through,
but
it's
also
not
the
most.
It's
not
the
deepest
sort
of
explanation
of
what
the
purpose
of
all
these
different
pieces
are
for
and
what
they
actually
do.
A
A
The
Co
general
asks
is,
you
can
think
of
it
as
multiple
levels.
There
actually
is
quite
a
bit
of
stuff
that
occurs
at
the
architecture
neutral
layer,
so
this
is
things
that
are
sort
of
sitting
way
up
at
the
base
Omar
layer.
This
is
an
extensible
class
by
the
way,
but
there
is
also
a
fair
bit
of
specialization
that
occurs
for
each
for
each
architecture
that
were
that
we're
dealing
with
and
that's
actually
to
be
expected.
A
So
the
main
purpose
of
the
codes
inner
class
is
to
be
sort
of
the
overall
Orchestrator
for
taking
Al
and
then
turning
it
into
machine
instructions
that
can
ultimately
be
executed
on
the
target
architecture.
As
I
said,
it
really
inherits
a
lot
of
functionality
from
the
the
class
above
it.
If
you
go
and
look
at
our
code
in
the
codes
in
directory
code,
then
/om
our
code,
generator
HPP
you'll,
see
that
it's
got
an
awful
lot
of
functions
in
there.
A
There
is
sort
of
some
comments
in
there
that
try
to
carve
that
up
into
a
different
sort
of
sets
of
of
tasks
so,
for
example,
things
to
do
with
register
assignment
things
to
ask
to
answer
questions
about
capabilities
things
to
do
with
global
register
assignment
things
to
do
with
tree
evaluation,
that
sort
of
thing,
there's
data
structures
and
all
kinds
of
things
under
there.
So
you
get
a
sort
of
a
rough
sense
of
that,
as
I
said
before.
I
think
that
a
lot
of
this
actually
can
get
cleaned
up.
A
It
also
those
things
like
answering
questions
about
the
what
a
code
generator
is
capable
of
doing
so.
The
example
of
God
here
is:
you
can
ask
like
an
optimizer,
can
ask
the
code
generator
if
the
code
generator
is
capable
of
doing
something
optimized
for
square
roots
and
in
some
cases
it
would
leave
it
alone,
not
optimize
it.
Knowing
that
the
back
end
is
going
to
take
care
of
it.
A
A
Another
important
class
is
machine
class
class
and
it's
real
purpose
is
to
provide
an
architectural
description
of
the
register
file.
So
what
registers
are
available
on
a
particular
processor
and
and
and
how
do
you
kind
of
go
about
manipulating
and
using
those
registers?
So
it
also
contains
things
to
do
with
register
assignment.
So
how
do
you
choose
the
debts
of
during
register
assignment?
A
The
question
is
going
to
be
asked
when
you're
coming
upon
when
you
have
to
assign
a
register
to
an
instruction.
What
is
the
best
register
sign
at
this
point
and
the
way
that's
the
way
that
things
are
implemented
is
of
the
machine
class.
You
know
contains
a
contains,
a
method
that
basically
answers
that
question.
A
A
A
The
other
thing
that
it
that
it
does
is
the
different
register
sign.
There
are
multiple
register
signers
that
are
available
there.
There
are
global
register
signers
and
there
are
local
register
signers.
The
this
particular
class
is
responsible
for
answering
the
questions
of
those
register.
Signers
might
ask
about
how
many
registers
are
available
and
what
the
ranges
are
and
that
sort
of
thing,
so
it's
usually
provided
in
a
table
form.
So
that's
it
for
the
for
the
machine
class.
I
guess
one
thing
I
should
have
mentioned
here
as
well.
Is
that
what
it?
A
Ok
excuse
me,
so
the
next
two
slides
actually
you've
already
seen
before
there
and
so
I-
guess
that
you
just
sort
of
consider
them
to
be
a
recap.
So
the
pre
evaluation
is
a
fairly
important
phase
in
the
code,
generator
code
generator
and
it
actually
involves
a
number
of
different
little
steps.
But
the
real
objective
of
peer
evaluation
is
to
really
produce
native
instructions
for
various
il
trees.
A
We
called
an
instruction
selection
and
what
we're
really
doing
is
flattening
a
tree
into
a
into
a
stream
of
instructions
and
the
the
word
evaluate
when
we
use
that
use
that
word.
What
we
really
mean
is
that
we're
generating
instructions
that,
when
you
execute
those
instructions,
it's
going
to
cause
the
value
of
the
tree
that
you're
evaluating
to
appear
in
a
virtual
register
and
the
active
register
of
a
true
evaluation.
It
doesn't
care
about.
It
doesn't
have
any
notion
of
a
limited
set
of
registers.
A
It
really
just
uses
whatever
virtual
registers
are
needed,
and
the
assumption
is
that
register
assignment
real
register
assignment
later
is
going
to
come
along
and
make
sure
that
the
the
limited
set
of
real
registers
available
on
an
architecture
are
going
to
map
onto
that
virtual
I.
Don't
know
that
until
an
8-foot
infinite
set.
Excuse
me
having
trouble
talking
tonight.
A
So,
if
a
so,
if
the
node
produces
a
result,
that's
consumed
by
other
nodes,
then
that
virtual
richer
is
going
to
represent.
That
result.
So
I
think
I
just
said
that
so,
okay,
so
the
way
that
the
nodes
are
generally
evaluated
is
that
the
children
go
first,
you
do
a
recursive
post
order.
Traversal
I
showed
an
example
of
that
in
the
presentation
a
couple
of
weeks
back
then,
once
a
virtual
register
is
produced,
you
sort
of
set
that
register
on
a
node
and
then
that
and
that
that
register
really
becomes.
A
A
An
evaluator
again
is
something
that'll.
Take
the
that
note
that
opcode
and
turn
it
into
a
sequence
of
instructions
and
every
code
generator
is
responsible
for
providing
evaluators
for
all
those
codes.
It's
very
very
unlikely
that
any
code
generator
is
going
to
share
an
evaluator
with
another
code,
generator
they're
that
specialized
to
that
particular
architecture
and
I.
Think
as
we'll
see
when
we
start
looking
at
arm
64,
this
is
really
where
the
bulk
of
the
work
is
going
to
be
in
producing
these
evaluators,
and
some
evaluators
are
fairly
trivial.
A
Others
can
actually
get
fairly
complicated,
like,
for
example,
with
calls,
and
that
sort
of
thing
so
just
to
give
you
sort
of
a
quick
tour
of
what
kinds
of
evaluators
there
are
and
where
they
generally
live
in
the
different
code
generators
there's
a
file
called
tree
evaluator
or
cross
cultural
value
as
well.
It
really
contains
a
lot
of
a
very
general
generic
node
evaluator.
So,
for
example,
things
like
BB
starts,
or
you
know
some
fairly
simple
up
simple
nodes
as
well.
A
Control
flow
of
elevator
really
contains
of
things
that
have
anytime
you're,
evaluating
something
that
will
generate
a
a
branch
or
some
kind
of
control
flow.
This
is
typically
where
it
ends
up,
so
it
contains
things
like
ifs
branches.
If
you've
got
switch
statements,
if
you've
got
things
that
generate
or
control
exceptions,
you
could
go
to
stop
they
all
sir
to
live
in
the
control
flow.
A
Evaluator
I
should
point
out
that
for
any
of
these
evaluators,
it's
really
just
sort
of
a
logical
classification
of
these
things,
there's
no
special
properties
or
special
powers
that
something
gets
by
being
in
one
file
or
another.
It's
just
a
matter
of
grouping
them
together,
and
it's
really
just
to
help
you
as
you're
sort
of
navigating
around
the
code
base
where
to
look
for
a
particular
evaluator.
A
Fp3
evaluator
typically
contains
floating
points
evaluation
code,
so
we
tend
to
stick
it
all
in
there.
Binary
evaluator
contains
evaluators
for
binary
operators,
so
adds
some
subtracts
multiplies
that
sort
of
thing.
There
typically
is
a
yearly
evaluator
as
well.
I,
don't
list
it
here,
but
there's
usually
a
yury
evaluator
for
things
like
negation
and
and
other
sort
of
operations
that
deal
with
that
and
then
through
sort
of
a
helper
class
that
that
is
available.
That
helps
you
generate
the
most
efficient
code
for
a
particular
architecture,
and
you
typically
write
this
per
architecture.
A
But
what
it
does
is
it
sort
of
analyzes
what
so
in
the
case
of
a
binary,
commutative
analyzer,
it
analyzes
commutative
operators,
so
things
like
ads
or
multiplies,
and
it
looks
at
what
is
the
best
way
of
generating
an
instruction
for
a
particular
operation
so
nor
it
understands
that
oh
I
don't
have
to
load.
This
particular
parameter
because
I
have
a
register
memory
form,
and
this
is
the
left,
and
this
is
the
only
reference
of
that
load.
A
So
I,
don't
I,
know
I,
don't
need
to
spray
into
a
register,
so
I
can
basically
use
the
register
memory
form
directly,
or
it
knows
that.
Well,
there's
actually
reverse
from
this
instructions
like
a
next
reverse
the
children,
because
it's
the
communitive
operation
and
I'll
get
better
encoding
that
way
so,
depending
on
the
architecture,
there's
lots
of
things
that
can
actually
happen
in
here
as
well.
A
So
one
of
the
key
building
blocks
of
the
output
from
the
code
generator
is
our
instructions,
so
this
is
actually
a
fairly
interesting
hierarchy,
it's
and
so
what
it
is,
what
they
are.
It's,
basically
a
dynamically
polymorph
hierarchy,
but
but
the
base
class
of
all
the
instructions
is
really
an
extensible
class.
So
what
we've
done
is
we
create
a
TR
instruction,
concrete
class
that
contains
func,
basically
functionality
that
all
instructions
in
omar
use
and
it's
specialized
by
the
target
architecture
and
your
particular
language
runtime?
A
So
in
the
case
of
Java,
if
you're
working
on
something
core,
Java
Java
can
actually
provide
in
this
base
class,
its
own
sort
of
specializations
and
then
basically,
what
that
forms
is
a
TR
instruction
base
class
and
then
your
for
a
particular
code.
Generator
can
come
along
and
create
instruction
kinds
that
really
derive
from
that
base
class
and
and
those
are
actually
dynamically
polymorphic.
So
I'm
not
actually
100%
familiar
with
that.
A
A
A
We
have
like
a
main
line:
inline
stream,
and
then
we've
got
an
out
of
line
stream
and
I'll
talk
about
the
other
one
stream
a
little
bit
later,
but
for
all
intents
and
purposes
when
you're
actually
creating
and
evaluating
nodes
you're,
actually
evaluating
to
this
inline
stream
and
the
identity
of
a
particular
instruction
is
further
refined.
By
associating
an
instruction
opcode
with
it,
so,
for
example,
in
the
case
of
a
single
register,
form
instruction,
there
could
be
multiple
nodes
that
there
could
be
sharing.
A
There
could
be
multiple
op
codes
that
can
be
associated
with
that
like,
for
example,
it
could
be
a
negation
or
it
could
be.
It's
a
push
for
like
push
out
code
or
something
like
that,
and
the
other
responsibility
of
the
instruction
of
a
particular
instruction
kind
is
that
it
really
needs
to
orchestrate
the
register
assignment
for
that
instruction
and
and
binary
encoding
of
that
most
code.
Generators
in
Omar
right
now
follow
this
kind
of
model,
something
like
the
Z
code.
Generator
though
they
tend
to
do
things
a
little
bit
differently.
A
There
they've
actually
gone,
and
you
know
they
they
could
have
register
assignments.
That
is
that
works,
and
all
that,
like
they
have
a
single
path
of
a
single
set
of
functions
that
work
on
all
the
different
kinds
of
instructions.
So
you
will
see
that
there's
a
fair
bit
of
redundancy,
if
you
don't
do
it
that
way,
so
the
way
that
they've
done
it
on
on
these,
actually
a
you
know
sent,
does
tend
to
save
on
the
logic
and
comes
up
some
of
the
redundancies
that
that
would
be
present.
A
A
Okay,
so
the
opcodes,
so
the
opcode
really
describes
the
function
of
an
instruction
and
it
is
often
mapped
to
a
real
processor
instruction,
so
an
add
or
multiply
or
divide
something
like
that
or
a
call,
but
it
can
also
be
mapped
to
a
pseudo
instruction.
So
these
are
things
that
don't
really
escape
out
into
the
egg.
We
won't
actually
get
binary
encoded,
but
they
have
special
meaning
in
the
instruction
stream.
So
you
can
so
some
of
the
things
some
of
the
metadata
you
can
associate
with
an
instruction
opcode.
They
all
have
properties.
A
So
you
know
answer
questions
like.
Is
this
a
branch
off?
Is
it
a
record
form
they
all
have?
If
there
are
real
instructions,
they
will
actually
have
a
binary
representation,
and
then
they
also
have
some
printable
mnemonics
that
are
used
when
you're
writing
outcome.
Log
files
and
stuff,
like
that,
so
any
time
that
you're
describing
an
instruction
opcode
you're
going
to
have
to
provide
all
of
these
different
things
now
I
mentioned
civil
instructions.
So
what
these
really
are
our
display,
folders
or
all
of
their
macro
instructions?
A
A
You
can
create
a
branch
that
goes
to
that
label
or
things
for
describing
the
basic
block
entry
or
the
entire
procedure
entry,
or
in
the
case
of
a
macro
instruction,
and
in
the
case
of
Java,
you
could
have
something
like
a
write
barrier
instruction
that
little
tend
to
happen
with
the
write,
very
instructions
that
they
tend
to
have
a
lot
of
logic
associated
with
it.
So
in
order
not
to
pollute
the
the
trees
or
the
struction
stream
too
early,
you
know
we
basically
use
a
compound
right
barrier
pseudo
instruction
that
gets
expanded
out
later.
A
And
lots
of
the
information
that's
associated
with
a
particular
opcode
is
actually
in
a
table
format,
and
what
that
means
is
that
you'll
find
that
there's
a
big
massive
property
table,
usually
that
indexed
by
the
opcode
binary
encoding,
is
the
same
way.
There's
like
a
binary
representation
table
that
gets
indexed
by
the
opcode
and
same
thing
with
the
names
of
these
different
things.
Now
the
generation
of
these
tables
is
really
depends
on
the
code
generator.
A
A
A
Okay,
so
one
of
the
components
of
an
of
an
instruction
often
is
some
kind
of
an
addressing
expression
or
a
shortened
addressing
operand
and
the
representation
of
an
addressing
mode
on
a
target
processor
can
be
achieved
through
a
memory
reference,
and
this
is
typically
very,
very
special
life
to
a
particular
forces
or
architecture,
because
the
addressing
modes
on
those
different
processors
are
typically
different.
So
just
an
example
of
what
a
of
what
a
addressing
mode
might
look
like.
A
You
could
have
a
form
of
an
instruction
of
an
addressing
mode
that
has
a
base
address,
plus
some
stride
times
an
index
plus
some
displacement,
and
you
would
use
that
form.
For
example,
when
you're
indexing
into
a
linear
array
or
a
linear
piece
of
memory
right
so
depending
on
the
architecture
you're
going
to
find
different
addressing
modes
and
therefore
the
memory
references
are
all
going
to
are
all
going
to
be
different.
A
A
The
other
thing
that
the
memory
reference
is
responsible
for
is
for
orchestrating
the
evaluation
of
a
node
and
of
a
no-bid
operates
on
memory
so,
for
example,
some
kind
of
a
load
or
perhaps
even
a
store
and
it,
but
by
providing
that
kind
of
evaluator
it'll
produce
a
memory
reference
that
an
instant
that
you
can
hang
on.
Other
instruction,
that's
in
the
that's
in
a
very
correct
form
and
perhaps
more
importantly,
the
most
efficient
form
of
addressing
modes
for
that.
So
that
particular
kind
of
evaluation.
So
you'll
see.
A
If
you
look
across
all
the
memory
references
on
all
the
different
architectures
that
they
have
a
form
we
were,
we
I
think
it's
compartment
and
they've
all
use
the
same
name,
I,
believe
it's
populate
memory
reference
and
you
basically
pass
it
a
node
and
it
just
sort
of
recursive
walk
down
that
node
and
it
actually
go
and
produce
the
most
efficient
memory.
Reference
for
that
particular
kind
of
addressing
expression,
you're
trying
to
you're
trying
to
do
there.
A
And
then
you
take
this
memory
reference
and
where
it's
really
only
used.
As
of
the
operand
of
an
instruction,
I
can't
really
think
of
anything
off
the
top
of
my
and
where
every
reference
is
not
used
in
any
other
context,
been
run
to
an
instruction
and
again
it
understands
for
a
particular
architecture.
The
requirements
for
forming
an
addressing
mode
and
the
limitations
about
addressing
mode
as
well
and
by
when
I,
say
limitations.
I
mean
things
like
if
in
some
architecture
and
you're
doing
some
kind
of
a
base
plus
displacement
form.
A
There
might
be
a
rule,
for
example,
that
the
base
register
always
has
to
be
gr
2
or
something
like
that.
So
that's
the
kind
of
thing
that
I
memory
reference
but
know
when
it's
actually
getting
encoded
and
the
memory
reference
also
has
to
be
able
to
do
register
assignment
and
and
to
encode
itself
understand
how
I
need
to
get
encoded
in
instruction
forms.
A
Register
is
another
important
component
of
of
instructions
like
as
an
operand
for
an
instruction,
so
the
the
main,
concrete
representation
is
a
ter
register,
expensable
class,
so
so
that
the
the
ter
register
base
class
really
represents
two
different
things.
So
it's
basically
the
it's.
Basically,
the
root
of
the
whole
register
hierarchy
that
you
might
want
to
go
from,
but
it
also
represents
these
pseudo
virtual
registers
that
we've
been
that
we've
been
talking
about.
So
it's
a
register
that
doesn't
necessarily
it
isn't
a
real
machine
register.
A
It's
something
it's
an
artifact
of
the
of
the
evaluation
process,
so
it
is
a
bit
overloaded
there.
So
it
says
here
it's
an
abstract
representation
of
my
machine
register.
They
can
have
different
kinds,
so,
for
example,
this
is
a
general
purpose
register.
This
is
a
floating
point
register.
This
is
a
condition
code
register
that
sort
of
thing.
If
you
look
in
clear
River,
where
there's
I
think
it's
a
register
constants
and
code
gen
register
constants,
but
HPP
that
will
sort
of
give
you
a
very
large
enum
of
what
the
various
kinds
are
that
are
available.
A
You
settle
register
and
therefore
that
register
now
dead
and
important
things
can
happen
from
that.
The
base
classes
also
maintain
the
backing
storage.
In
so
backing,
storage
is
sort
of
a
very
old
IBM
term
for
for
basically
still
still
space
or
for
for
register.
So
when
a
register
cannot
be
represented
in
a
register,
a
value
can't
be
register
represented
in
a
register.
It
has
to
be
stored
somewhere
and
we
store
it
internet,
that's
basically
a
spill
and
and
the
the
place
that
we
end
up
story.
A
It
also
has
a
link
to
for
example,
though,
if
it
actually
is
to
find
your
real
register,
it's
going
to
have
a
link
to
that
real
register
in
this
in
this
base
class
too
right.
So
once
you
have
this
base
class,
you
can
actually
start
to
derive
things
from
it
like
dynamically
polymorphic
things
from
it.
So,
for
example,
a
real
register
is
really
just
a
specialization
of
this
base
class
and
and
and
what
the
real
register
is.
It's
just
a
representation
of
a
real
register
on
a
target
right.
So
this
represents
GPR
a
right.
A
It
represents
something
like
that,
but
also
those
things
about
that
are
important
to
register
assignment.
So
it
knows
it's
state
I
know,
I,
know
that
it's
a
sign
or
I
know
that
it's
been
spelled
out
or
law
for
freedom
and
latch,
and
at
some
point
we
can.
You
can
probably
talk
about
register
assignments
in
more
detail,
but
I
can
I,
guess
I'll
just
quickly
go
through
what
those
different
states
actually
means
inside
since
I
just
mentioned
them
here
for
a
real
register
to
be
assigned.
A
Actually
anything
about
that
one,
because
I'm
not
I,
don't
quite
recall
the
contact
stays
in
the
context,
I'm
a
real
register.
What
that
actually
means
locked
means
you
cannot
use
that
will
register
for
assignment
under
any
on
under
nearly
any
circumstance,
free
need.
That's
available
and
unlatched
is
sort
of
a
special
state
of
a
register
that
is
used
on
instructions
that
I've
got
multiple
registers
and
you
and
as
you
are
it's
possible
that
a
register
can
actually
become
free
in
the
middle
of
an
instruction
right.
A
That
is
by
associating
two
32-bit
registers
together,
that
represent
about
64,
good
value
and
the
way
that
you
ensure
that
those
two
32-bit
haves
are
you
know
are
considered
together
is
with
a
the
register
pair
I
believe
that
there's
also
some
uses
of
this
on
some
coding.
Point
architectures
as
well,
I'm,
not
quite
familiar
with
that.
A
That's
used
in
instruction
right,
so
this
is
where
you
can
tell
where
you
can
basically
specify
that
if
I'm
using
this
particular
instruction-
and
this
instruction
expects
that
the
shift
length
is
going
to
be
in
a
certain
register
right
like
it's
going
to
be
in
like
gr
0,
then
this
is
how
this
is
a
mechanism
that
you
use
to
in
tune
to
enforce
that.
So
what
you're
really
doing
is
you're
telling
the
register
slinger.
This
is
the
can
see.
A
These
are
the
conditions
that
must
be
true
like
before
and
after
you
assign
the
registers
for
this
instruction.
So
we've
got
the
notion
of
preconditions
so
sort
of
the
state
that
has
to
happen
before
the
instruction
and
then
post
conditions,
the
state
that
must
be
true
after
an
instruction
and
typically
every
instruction.
A
This
is
true.
I
know
it's
true
in
x86
and
lis
and
100%
sure
if
it's
true
and
power
and
arm
yet,
but
almost
every
instruction,
you
can
even
hang
a
register
dependency
on
I.
Think
power
still
uses
depth
form
instructions
like
you
actually
to
have
a
specialized
instruction
form,
that's
that
and
that
you
can
hang
a
register
dependency
on,
but
anyhow
you
dissolute
leo,
so
you
there
should
be
a
form
that
you
can
find
where
you
can
hang
a
register
dependency
on.
A
If
you
need
it
and
the
way
these
actually
look,
is
you
basically
it's
sort
of
a
mapping
of
a
virtual
register
to
a
real
register
right.
So
you
know,
GPR
836
has
to
be
assigned
to
do
like
GPR.
Verb,
sorry
has
to
be
fine
to
gr0
right
in
in
there
go
register,
and
you
can
really
sort
of
build
up
these
sort
of
mappings
of
that.
But
we
also
have
some
sort
of
special
pseudo
registers
that
that
you
can
use
as
well.
So
I've
got
two
of
them
here,
so
probably
the
most
common
ones
here.
A
It
just
find
it
a
real
register
and
make
sure
that
it
defined
at
this
point
and
what
why
you
might
think
you
may
be
wondering
what
that's
even
useful,
Hall
and
but
there
are
very,
there
are
some
circumstances
in
the
code
generator
where
you
have
to
carefully
manage
the
spill,
State
or
register,
and
the
the
biggest
example
I'll
give
you
here
and
that's
something
we're
going
to
have
to
watch
out
for
us
baby.
As
we
start
doing.
A
A
lot
of
these
evaluators
is
that
the
biggest
assumption
in
the
code
in
the
backend
is
that
you
don't
introduce
control
flow
right.
If
you
start
introducing
branches
in
that,
the
local
register
signer
on
any
architecture
doesn't
know
anything
about
control
flow,
it
can't
follow
it
can't
maintain.
It
doesn't
know
that
okay,
this
register
was
spilled
on
this
path,
but
it's
not
spilled
on
that
path,
and
it's
not.
It
cannot
maintain
that
state
at
all.
A
So
linkage
itself
is
actually
a
concrete
extensible
class,
but
you
can
then
derive
by
the
different
processor
architectures.
You
can
derive
different
linkages
from
that.
So
a
big
example
would
be
system
link.
Is
your
seed
linkage,
something
like
that
and
it's
basically
all
the
rules
that
need
to
be
followed
in
order
to
implement
system
linkage
for
that
particular
processor.
You
can
also
do
things
like,
like
in
the
case
of
Java,
there's
something
to
look
at
code
before
in
open
j9,
there's
like
private
linkage
in
that.
A
So
you
can
really
build
up
your
own
kind
of
linkage
here
and
then
it
can
get
even
more
complicated
like
that.
I
could
be
other
look
at
the
V
on
the
V
architecture
and
zico
again
different
kinds
of
system
linkage
depending
upon
the
operating
system
that
you're
on
better
lessers
at
linux
and
that
sort
of
thing,
so
things
can
actually
get
quite
quite
complicated.
A
So
the
base
class
really
describes
the
linkage
linkage
property.
So
things
like
you
know:
what
more
do
you
have
to
evaluate
arguments
you
know?
Do
you
call
clean
up?
The
colleague
stack
clean
up
that
sort
of
thing
it's
responsible
for
generating
the
prologues
and
epilogues
for
a
particular
methods.
It
has
to
map
the
arguments
and
the
locals
of
a
method
onto
the
stack,
so
you
know
buying
the
stack
frame.
A
A
Which
parameters
are
passed
on
the
stack
and
how
do
they
get
there,
and
even
things
like
if
you've
got
something
that
splits,
if
you've
got
something,
that's
split
between
the
stack
and
register?
How
do
you?
How
do
you
maintain
that?
And
how
do
you
pass?
You
know
how
do
you
handle
barge
and
all
that
sort
of
thing,
so
it's
a
it
can
be
a
fairly
complicated
class
for
sure
and-
and
it's
usually
one
that
will
take
a
bit
of
care
and
a
bit
of
time
to
get
right.
A
A
So
I
guess
for
some
lighter
fare
now,
so
you'll
undoubtedly
see
if
you
start
looking
at
other
code
generators
and
even
the
32-bit
arm
that
there's
sort
of
this
notion
of
things
called
snippets.
This
is
actually
a
fairly
old
concept.
It's
actually
one
of
the
the
very
earliest
means
that
we
had
in
the
code
generator
for
handling
sort
of
exceptional
circumstances.
A
The
way
that
we've
traditionally
done
it
is
with
something
called
call
the
snippet
and
they're,
mainly
characterized
by
the
fact
that
they
are
all
hand
coded
instructions
which-
and
that
means
that
they're
not
register
signs,
so
I
need
to
create
an
instruction
I
created,
knowing
that
the
source
register
is
going
to
be
gr2
and
the
target
register
gives
me
gr8
and
that
kind
of
stuff
and
they're
actually
emitted
fairly
late
after
the
binary
encoding.
It's
basically
just
run
through
and
write
them
out.
A
It's
actually
a
fairly.
You
can
actually
write
some
fairly
compact
code
that
way-
and
you
know
precisely
what's
going
to
happen,
but
these
days
there's
actually
better
ways
of
of
emitting
code
out
of
line.
So
these
are
sort
of
relegated
to
sort
of
a
I
guess
you
can
say
they're
mostly
deprecated
in
most
architectures,
but
they
are
still
used.
It's
just
a
fair
bit
of
work
to
convert
them
into
something
something
new.
So
that's
going
to
happen.
You
know
hopefully
over
the
next
five
years
or
so,
but
it's
better
there
you're
going
to
see
them.
A
So
the
thing
that
most
could
energy
these
days
are
things
called
out
of
law
instructions.
So
this
is
where
we
actually
create
a
secondary
instruction
stream
that
can
be
evaluated
or
you
can
add
instructions,
and
you
know
it
basically
handles
the
exceptional
code
paths,
but
they
actually
provided
more
power
in
the
Sun
side,
you
can
actually
evaluate
a
node
on
that
stream
right,
so
I
don't
actually
have
to
manually,
go
through
and
and
insert
instructions
one
at
a
time
in
a
very
precise
encoding.
A
I
can
just
simply
evaluate
a
note
on
that
stream
and
it
will
create
all
the
instructions
it
needs
to
do
that
or
that's
super
useful
is
with
calls,
because
if
you
didn't
have
the
ability
to
evaluate
a
node,
that
was
a
call
out
of
line,
and
you
wanted
to
do
that
call
with
a
snippet.
You
would
actually
have
to
go
figure
out.
A
The
linkage
and
you'd
have
to
do
every
little
step
manually,
which
it
would
be,
which
would
be
a
very
error-prone
and
very
tedious
process,
so
so
that's
sort
of
what
motivated
these
in
the
first
place,
they
are
register
signs
most
of
the
register,
signer
thing
and
the
different
architectures
are
smart
enough
to
handle
spilling
that
occurs
like
in
the
out
of
line
path
and
and
not
in
the
main
length
path
that
will
branch
through
it.
So
I
said
before
that
the
register
signer
isn't
smart
enough
to
handle
control
flow.
A
The
one
little
gotcha
with
this
is
that
the
way
that
you
determine
the
target
like
we
determine
where
you're
going
to
be
evaluating
instructions
on
you
have
to
do
this
programmatically
right.
So
you
use
this
to
encode
gen
and
you
basically
have
to
say,
switch
the
instruction
stream
to
the
mainline
one
or
the
other
line.
So
you
basically
control
where
things
are
going,
not
a
big
deal.
A
And
then
the
last
thing
I
guess
I
wanted
to
mention
was:
is
the
debug
class
we
have
the
the
debunk
story?
Is
it
is
that
we
don't
have
the
cleanest
solution
anymore,
the
API
and
there's
a
lot
of
reasons
for
that.
But
if
you,
if
you've
ever
looked
in
one
of
the
debug
classes
on
a
particular
in
a
code,
generator
you'll
find
there's
a
lot
of
stuff
in
there.
A
You
know
those
are
the
needs
of
doing,
and
that's
not
I
mean
that's
not
such
a
big
deal.
But
it's
it's
just
a
little
bit
tedious
to
do
and
and
the
API
is
great,
we've
actually
deprecated
the
API.
We
don't
really
want
to
you're
adding
a
lot
of
stuff
on
to
the
debug
API.
We
do
know
that
it
needs
to
get
reaaargh
affected
at
some
point.
It's
just,
unfortunately,
just
not
the
it's
just
not
that
high
on
the
priority
list
anymore.
So,
okay,
so
I
think
that's
my
last
slide
yeah.
A
A
A
So
clonus
on
was
saying
that
the
armed
32gb
code
was
no
longer
used
and
you
removed
from
the
code
repository
okay,
that's
interesting,
I'm
I!
Guess
I'm
somewhat
surprised
to
hear
that,
because
ultimately,
it's
still
going
to
have
to
I
mean
there
must
be
other
means
that
it
uses
for
printing
instructions,
for
example,
or
knowing
how
to
describe
how
to
print
the
registers
and
the
memory
reference
and
that
kind
of
stuff.
So
I
haven't
really
explored
that
too
much
on
arm,
but.
A
So
James
asking
how
two
jumps
work.
Does
it
take
multiple
passes
to
figure
out
the
distance
needed
to
jump
so
so
there
is
a
right.
So
the
way
that
we
handle
branches
and
where
they
need
to
go
is
with
what
we
call
three
locations
and
relocation
processing
is
actually
so
we
as
you're
generating
instructions.
A
So
relocation
processing
is
is,
is
the
thing
that
accomplishes
that
if
you
look
at
relocation
processing,
it's
actually
fairly
complicated,
it's
a
lot
more
complicated
than
you
might
think
it
should
be,
and
the
reason
for
that
is
because
it
does
more
than
just
serve
the
branch
relocations.
It
also
does
a
lot
of
the
stuff
for
ahead
of
time,
compilation
as
well,
where
there's
other
parts
to
code
that
need
to
have
relocations
associated
with
them.
So
it
looks
a
little
bit
more
busy
than
it
perhaps
actually
is
so.
A
A
And
around
I
think
6
p.m.
Eastern
I'll
help
and
check
on
that.
This
makes
sure
everyone
is
ok
with
that,
but
the
next
step
I
think
we
need
to
take
here
is
the
sort
of
because
we've
got
so
a
lot
of
different
people
here
and
there's.
Potentially,
a
lot
of
overlap
is
from
the
work
that
we
need
to
do
here.
A
I
think
what
I'll
do
is
just
take
some
of
the
experience
that
I
have
and
sort
of
carve
off
pieces
that
I
think
can
be
done
independently,
and
then
we
can
all
you
can
all
discuss
about
who's
going
to
do
what
work
so
that
we
don't
end
up
stepping
on
every
on
each
other's
toes
because,
like
for
example,
we
all
can't
work
on
the
linkage
class.
At
the
same
time,
we
all
can't
do
in
other
ways.
A
Is
you
know
something
at
the
same
time,
and
there's
also,
you
know
key
infrastructure
pieces
that
need
to
be
built
first
right
like,
for
example,
start
building
up
the
code
generator
class.
The
machine
class
is
very
important
right,
so
the
very
important
things
like
that
they
provide
some
of
the
mechanisms
that
we're
going
to
need
need
to
be
developed
as
well.
A
A
Okay,
all
right,
so
I've
recorded
this
so
I'm
going
to
post
it
up
on
an
hour
eclipse
of
our
YouTube
channel
in
case.
Anyone
who
didn't
get
to
hear
me
get
through
this
wants
to
do
this.
I'm
I'm,
hoping
that
in
the
future
we
can
drill
down
to
much
greater
depth
on
some
of
these
other
topics,
for
example,
register
assignments
or
even
the
relocation
processing
that
kind
of
stuff
for
metadata
generation
whatever
so,
but
but
for
now,
I
think!
That's!
That's
it!
So
thanks!
Everyone
for
joining
and
I'll
talk
to
you
again
soon.
Hi.