►
From YouTube: 20210923 OpenCPI and FPGA Work
Description
Can OpenCPI work for ORI's FPGA work on Phase 4 Ground and Space? We talk details OpenCPI's Aaron Olivarez.
A
B
B
A
Sure
so
opencpi
is
a
framework
and
it
stands
for
component
portability
infrastructure
and
it
tries
to
deal
with
both
both
the
general
purpose,
processor
and
an
fpga
or
any
processing
element.
So
we've
in
the
past
have
considered
you
know
also
including
gpus,
and
we
worked
with
opencl
for
a
little
bit.
But
it's
not
it's.
It's
not
a
feature
yet,
but
it's
still
under
consideration
and
what
it
is.
A
Is
it's
similar
to
gnu
radio
in
that
you
break
down
components
based
by
by
functionality,
but
instead
of
in
gnu
radio,
the
digi,
you
know
you're
you're,
targeting
the
the
processor
and
it
doesn't
go
any
doesn't
go
anywhere
else.
So
what
would
we
try
to
do
with
our
components?
You
can
target
them
for
the
fpga
and
or
the
general
purpose
processor,
and
one
of
the
features
of
opencpi
is
a
platform
portability.
A
A
A
Another
advantage
of
opencpi
is
that
we
have
a
remote
execution
model,
there's
different
ways
to
deploy
applications.
There's
a
standalone
deployment
where
everything's
running
on
on
the
platform
itself.
There's
a
network
mode
execution
where
the
on
the
arm
you
mount
nfs
storage
and
allows
you
to
access
all
the
artifacts,
all
the
components
available
for
that
platform
and
run,
and
then
we
as
also
have
remote
remote
mode,
which
allows
you
from
a
development
host
to
essentially
run
applications
on
the
on
the
device
but
you're
executing
that
from
from
the
host
itself.
A
So
it's
kind
of
it's
not
it's,
not
partial
reconfiguration
that
we
do
on
the
on
the
on
the
fpga
fabric.
But
it's
close
where
we're
always.
You
know
stripping
away
the
the
bit
stream
and
loading
a
new
one
based
on
the
application
specifications
and
then
another
thing
that
opencpi
brings
to
the
table
is:
you
know,
applica
an
application
control
interface,
which
allows
you
to
manipulate
registers
from
the
software
side,
from
the
host
or
from
the
arm
on
the
fpga
itself
and
there's
a
lot
of
different
different
details.
A
And
I
know
some
of
you
guys
have
been
started
going
down
that
pathway
and
there
is
a
slight
learning
curve.
But
that's
why
yeah
I'm
one
of
the
it's
always
been
a
pain
getting
new
users,
not
necessarily
a
pain.
But
it's
difficult
to
get
new
users,
because
you
know
I've
been
working
with
opencpi
for
two
years,
but
the
the
open
cpi
has
existed
for,
I
think
over
dec
at
least
a
decade,
if
not
two
so
there's
a
lot,
there's
a
lot
to
learn.
B
A
Oh
yeah,
so
we
handle
because
of
our
platform
vendor
agnostic
and
platform
agnostic.
So
we
we
have
a
lot
of
examples
with
xylinks,
but
it's
not
limited
to
using
xilinx
fpgas.
So
we
kind
of
handle
that
those
tools
together,
because
we
have
we
use
incremental
compilation
where
you
have
your
component-
will
generate
a
net
list
and
then,
once
you
have
you
know,
we
call
an
assembly
is,
is,
is
a
bunch
of
components
on
the
fpga
they're
running
together
and
they'll
generate
the
bitstream
itself.
A
That
has
also
also
all
that,
other
you
know:
data
flowing
dma
engine
along
in
it
in
in
the
bitstream
itself,
but
as
so,
the
workflow
is
a
little
bit
different.
It's
not
you're,
not
using
vibato
directly.
We
call
the
bottle
in
the
background
and
a
lot
of
it
is
in
command
line
and
the
loading
of
the
bit
stream.
We
there's
a
kernel
module,
an
open
cpi,
kernel,
module
that
uses
the
fpga
manager,
depending
on
what
version
of
linux
you're
running
on
the
embedded
system.
A
B
A
So
we
do
have
direct
support
for
the
analog
devices
809361,
and
I
know
I've
been
following
you
guys
for
a
while.
You
guys
are
targeting
the
80-93-71
and
support
with
an
open
cpi,
for
that
is
slated
for
some
time
at
the
end
of
this
year
and
that
will
handle
the
the
transceiver
itself
and
then
it'll
pipe
the
you
know
the
adc
and
the
dac
into
open
cpi
so
that
it
can
be
consumed
by
by
the
components.
B
B
Yeah,
that
might
be
an
option
if
we
can,
because
all
the
great
work
by
andre
and
anshul
and
the
the
the
transmit
encoding
modulation
is
kind
of
not
being
utilized
from
over
over
the
air.
Yet,
even
though
it's
been
quite
mature
for
a
while,
so
it'd
be
good
if
we
can
get
to
the
point
of
testing
over
there
as
soon
as
possible.
Maybe
this
is
a
good
good
way
of
doing
that.
A
Yeah,
so
I've
been
looking
over
the
the
andre's
work
and
it's
very
extensive
and
very
impressive
and
looking
at
what's
the
quickest
way,
we
can
get
to
something
demonstrable
and
originally
I
I
before
I
had
taken
a
look
at
it.
I
was
looking
at
it.
You
know
we
can
break
it
apart
and
we
can.
We
can
test
each
component,
but
he's
already
even
he
has
unit
tests
for
that
already.
So
so,
currently,
what
I'm
I'm
looking
into
is
is
just
taking
that
ip
block.
A
C
C
C
A
C
A
C
C
From
what
I'm
reading
you
have
workers
right,
so,
for
example,
if
you
have
you
can
implement
some
function
with
with
a
worker
and
to
run
like
you
have
to
have
that
resource
or
that
platform.
For
example.
The
fpga,
I
think,
is
the
most
obvious
like.
If
you
don't
have
a
supported
platform
platform,
then
you
not
be
able
to
use
that
worker
right.
A
So
a
lot
of
our
components
that
currently
exist
try
to
trying
to
try
to
build
some
stuff
from
scratch
so
that
it
can
be
inferred.
But
there
are
there
are
times
where
we
want
to
leverage.
You
know
the
vendor.
You
know
ip
cores
that
are
available.
You
know
for
building
furs
or
whatnot,
but
so
yeah.
There
is
the
mechanism
where
you
can
have.
You
know
shadowing
implementations
of
workers
that
work
for
specific
fpga
architectures,
but
I
I
don't
know
if
that
answers
your
question
or
not.
A
A
I
think
we
talked
a
little
about
this
in
select
where
there's
a
control
plane
and
a
data
plane,
and
so
the
control
allows
you
to
you
know,
set
and
get
you
know,
properties
of
the
of
the
workers
that
are
on
the
fpga
fabric,
there's
also
some
metadata.
So
you
can,
you
can
read
back,
you
know
bit
stream
what
version
of
the
there's
a
uid
in
the
bit
stream.
A
So
you
know
what
bit
stream
you
have
loaded
on
the
fpga
and
that
that
is
uses
one
of
the
axi
general
purpose,
ports
on
between
the
fabric
and
the
arm,
processor
and
the
zinc,
and
then
for
the
data
plane.
We
use
the
high
performance
ports
and,
and
we
have
a
translation
from
axi
to
to
our
on-chip
communication,
the
scalable
data
plane
and
then
does
that
conversion
for
you
and
then
once
we
have
so
you
have
a
worker
working
on
hdl,
typically
there's
a
also
a
worker
on
the
general
purpose.
A
Processor,
that's
consuming
that
data
via
that
interconnect
and
then
you
you
can
do
whatever
you
need
to.
So
in
the
past,
when
I've
generated
waveforms
using
opencpi,
we
we
usually
hook
it
up
to
to
like
lib
zmq
and
then
pass
that
data
on
to
something
that
you
know
cares
about
it.
So
there's
different
ways
to
to
do
things.
A
Once
you
have
that
data
that
data
path
on
on
the
general
purpose,
processor
and
then
sometime
and
then
also
within
opencpi,
you
can,
you
can
run
your
application
away
from
the
platform
too.
So
you
can
you
also
because
it
supports
distributed
environment,
so
you're
not
tied
to
necessarily
just
one
device
you
can.
You
also
can
run
things
on
the
left.
You
know
if
you
have
a
laptop
nearby
that
has
an
x8664
or
and
then
you
can
also
have
workers
across
different
fpgas.
A
A
B
C
Yeah,
so
right
now,
the
way
I've
been
testing
is.
I
have
like
carefully
crafted
data
like
the
the
length
has
to
be
very
specific,
so
with
the
gsc
encoder,
it
will
sort
of
package
multiple,
like
ethernet
frames
and
sort
of
take
care
of
you,
so
you
just
basically
send
lots
of
data
and
it
will
sort
of
create
the
basic
frames
to
feed
the
thing.
C
So
to
answer
your
question:
it
can
be
random
data,
but
it
has
to
be
it
has
to
have
a
certain
length
and
that
that's
right
now,
the
only
limitation,
okay,
so
the
obviously,
if
you're
checking,
then
you
have
so
the
way
I've
been
checking.
I
run
the
new
radio
with
random
data
going
in
and
I
sort
of
tap
stuff
around.
C
A
A
You
know
just
read
a
file
and
then
write
a
file,
and
then
we
can.
We
can
check
the
check
check
to
see
whether
that
the
data
that
is
being
generated
or
is
valid
depending
on
what
what
you
have
instantiate
like
workers.
You
have
that
you
want
to
test.
So
there
is
there's
even
a
unit
test
framework
that
kind
of
handles
that
for
you
and
you
can
test
either
properties
or
parameters
and
a
parameter
is,
you
know,
build
build
time.
C
A
C
A
A
B
A
B
I
understand
it
correctly
that
you
could
basically
have
different
implementations
for
each
block.
So
one
thing
I've
wanted
to
do
for
a
long
time
is
to
have
a
an
end-to-end
simulation,
so
we
could
have
basically
python
high-level
models
for
bits
we
haven't
made
yet
and
then
later
we
can
fill
them
in
with
the
real
rtl.
Is
that
correct.
A
Yeah,
so
we
we
call
we'll
well
when
we
create
components,
we
encourage
you,
know
component
developers
to
generate
both.
You
know
so,
unfortunately,
right
now
we
don't
support
python
directly
as
as
a
worker
for
for
the
general
purpose,
processor
we
support
c
and
c
plus
plus,
but
yeah.
We
call
those
work
alikes.
So
so
so
a
component
is
basically
just
a
specification.
A
You
know
just
defining
the
ins
and
outs
and
the
types
of
configuration
you
might
do
and
then
a
worker
is
the
the
implementation
of
that
component
and
that
that
implementation
can
be
either
for
the
fpga
or
for
for
the
general
purpose
processor.
And
then,
when
you
generate
your
application,
you
can
you
can
pick
and
choose
where
you
want
that
to
run.
B
A
A
B
A
Oh
okay,
so
when
we,
you
know
so,
there's
three
types:
really:
three
types
of
development:
there's
the
application,
development
component
development
and
then
there's
an
osp
development
and
that
stands
for
open
cpi
system
support
project.
A
lot
of
people
use
the
term
bsp,
but
we
decided
to
create
our
own,
so
the
osp
development,
and
so
basically,
you
create
component
component
developer
components
that
an
application
developer
will
use
and
then
an
osp
developer
will
enable
new
fpga
platforms.
A
You
know
to
be
open,
cpi
compatible
and
as
far
as
every
osp
development,
there's
always
a
chain
of
of
proving
that
the
fpga
is
functional
to
to
its
ability,
and
one
of
the
first
stages
is,
is
being
able
to
hardware
acceleration
being
able
to
send
data
to
fpga
and
then
receive
data
to
fpga.
In
that
application
we
call
as
test
bias
and
and
that
there's
a
fpga
worker,
that's
in
in
the
fpga
that,
basically
just
you
know,
you
bias
it
to
a
certain
value.
A
A
C
Last
thing
I
was
doing
was
trying
to
get
the
dmv,
so
I
I
used
first
like
axi
light
accesses.
So
basically
each
four
byte
word
is
one
access
or
something
like
that,
which
is
you
know,
functionally
it's
nice,
but
it's
like
zero
performance
so
x
with
dma.
You
can
obviously
stream
a
bunch
of
data
and
then
the
next
thing
would
be
the
like.
A
C
A
A
Yeah,
you
can
quickly
get
to
a
point
where
you
can't
send
enough
data
to
to
fulfill
the
dax
need,
but
but
yeah
we
we
do
take
account
that
back
pressure
and
then
the
workers
has
a
handshaking
that
that
essentially
tells
the
processor
it's
like
hey.
I
can't
handle
this
much
data
or
it
could
say
the
opposite.
You
know
keep
sending
me
data
as
fast
as
you
can
type
of
thing,
but
but
yeah.
I
hope
that
answers
the
question.
C
C
C
A
A
We
re
we
configure
the
bit
stream
pretty
much
freely,
but
as
far
as
reconfiguration,
you
also
will
probably
want
to
reconfigure
the
arm
processor
as
well,
right
so
and
that
would
probably
stored
on
cue
spy
or
something
like
that
or
some
sort
of
other
storage,
so
that
that's
kind
of
a
little
bit
outside
of
the
scope
of
open
cpi.
We
do.
A
We
do
handle
a
lot
of
stuff
just
to
get
started
in
the
sense
where
we
pack,
we
use
this
like
a
pretty
generic
version
of
pedal
linux,
that
pretty
much
pre-built
by
by
the
vendor
and
or
through
the
pedaling
scripts
and
typically
the
way
we
run
it
is,
is
an
sd
card
mode.
But
you
know
there's
all
these
other
ways
that
you
can
configure
an
fpga
design
or
any
fpga
for
that
matter.
A
B
A
Yeah
and
yes,
fpga
hoarder,
so
I
have
all
these
different
types
of
fpgas
and-
and
you
know
trying
to
stand
up
on
like
each
individual
chart.
You
know
vivado
instances
yeah.
This
is
one
open
cpi
kind
of
like
opens
the
door
for
a
lot
of
people
who
have
fpgas
laying
around
in
in
at
their
home.
You
know
when
they
buy
just
a
simple
just
to
just
get
playing
around
with
it
quicker
type
of
thing.
B
B
So
the
receive
site's
a
bit
up
in
there
at
the
moment.
We
need
to
look
at
that,
so
I
know
michelle's
been
working
with
m17
group.
I
haven't
been
involved
at
all.
It
looks
interesting,
but
we
also
said
that
by
the
original
kind
of
architecture
they
receive
has
some
interesting
properties.
I
think
it's
like
400
narrowband
channels,
then
get
combined
so
yeah
there's
a
lot
of
work
on
the
safe
side
as
well.
It's
done
it's
blocked
out,
but
that
goes
back
to
the
kind
of
system
modeling
stuff
that
I
mentioned.
B
C
A
So
yeah
that's
been
brought
up
in
the
past.
How
can
we
get
a
good
new
radio
block
into
open
cpi?
I
mean
and
it
has
been
done,
but
there's
not
a
straightforward.
You
know
you
know
like
a
converter,
if
you
will
that's
been
generated,
but
but
yeah
it's
been
yeah.
There's
well,
there's
not
open
examples
of
it,
but.
A
Yeah,
actually,
we
do
have
some
examples
that
are
coming
coming
out.
I
don't
know
exactly
the
exact
timeline,
but
you
know
a
lot
of
sdr
frameworks.
Have
you
know
adsb
receiver
as
an
example,
or
that's
one
that's
coming
out
and
then
another
one
would
be
a
zigbee
receiver
type
of
thing
just
to
get
familiar
with,
with
how
components
and
workers
are
connected
and
stuff
like
that.
A
B
C
So
this
is
the
receiver
where,
like
there's
a
receiver
as
in
the
the
earth
part
there's
the
receiver
in
the
space
parts
like
the
space
part
is
the
thing
that
is
it's
harder
because
of
the
400,
something
channels
that
I
think
thomas
mentioned
right.
Yeah
like
the
earth.
One
is
probably
not
simple
simple
but,
like
you
can
use
like
off-the-shelf
stuff.
B
Well,
I
think
the
earth
one
they
have
to
have
so
that
the
space
receive
is
a
simpler
protocol,
so
be
using
older,
less
good
but
easier
technology.
So,
basically,
especially
the
forward
error
correction,
whereas
the
earth
receive
will
have
to
basically
undo
the
or
decode
the
dvds
dbb
s2x,
which
will
be
a
bit
of
work.
But
there
are
off
the
shelf
chips
that
can
do
that,
which
I
think,
while
they
looked
at
had
a
few
candidates,
they
could
basically
receive
it
so
yeah.
B
A
B
C
A
A
B
C
A
B
A
B
C
A
We
have
plans
of
upgrading
and
I
did
spend
a
little
time
to
see
if
the
scripts
that
we
have
will
generate
the
the
rcc
platform
would
work
so
there's
there's
still
more
work.
It
is
possible,
it's
not
it's,
not
something
huge,
but
but
right
off
the
bat
we
there's
the
version
that
we
support
is
2019.2.
C
C
C
C
C
B
C
A
Right
yeah,
it's
it's
usb
2.,
so
that
that's
if
you're,
getting
from
a
from
a
host
development
system,
getting
samples
and
or
sending
data
through
that
is-
is
kind
of
like
the
limiting
factor
of
it.
But
if
you're
generating
everything
from
or
majority
of
the
things
from
the
arm
and
the
fabric,
then
that's
not
really
a
problem.
You
can
leverage
the
the
capabilities
of
the
transceiver
itself,
but
yeah.
It
is
usb.