►
From YouTube: ORI FPGA Standup 12 July 2022
Description
DMA memory address bus error, comparison to PLUTO connections, and Remote Lab South construction and bacteriophage R&D (cross-posted)
A
We're
talking
about
a
variety
of
things.
First
of
all,
we've
had
huge
steps
forward
with
the
processor
side
environment.
So
what
we're
trying
to
do
is
allow
people
to
work
on
the
fpga
downlink
for
the
spacecraft
in
in
vitus
or
or
something
similar,
and
all
of
that
workflow
has
been
worked
out.
A
So
so
we
can
write
code
in
the
ide
for
the
zc706,
but
what
we
found
out
yesterday
and
the
day
before
the
day
before
we
really
didn't
know
what
was
going
on,
but
definitely
yesterday
it
was.
It
became
very
clear
that
the
zc
on
the
zc706
of
the
arv
9371
that
the
encoder
once
it's
hooked
up
in
the
hdl.
A
We
can't
access
it
through
dma.
So
we
get
a
bus
error.
This
bus
error
message
is
not
obvious.
Invite
us,
which
is
disappointing,
but
we
can
see
it
clearly
when
we
log
in
to
the
target
and
we're
not
really
sure
what's
going
on,
so
we
thought.
Maybe
it
was
because
the
the
encoder
was
in
the
amba
pl
part
of
the
device
tree
instead
of
under
axi,
but
it
looks
like
that.
A
That's
really
red
herring,
but
that's
not
the
case
because
very
similar
results
on
the
pluto
with
the
working
encoder
and
a
working
transmitter
that
it's
it's
almost
the
same
situation.
So
that's
that's
not
the
problem.
A
So
we've
done
something
in
the
process
to
to
make
it
impossible
to
use
dma
with
the
encoder
on
the
zc706,
when
I
think
it's
working
fine
on
the
pluto,
so
that's
where
we
were
at
as
of
last
night,
so
I
I
sent
along
at
least
in
slack
the
system
block
diagram
from
vivado
of
how
it's
hooked
up
on
the
zc706,
and
this
is
provisional,
because
we
we
hooked
up
like
the
the
slave
and
the
master
axi
stream,
and
we
hooked
up
all
of
the
signals
that
we
think
we
know
about
we're
concerned
about
a
signal
that
we
have
hooked
up
to
the
dac
fifo.
A
A
A
A
We
definitely
need
some
help
to
get
the
to
get
the
excellent
results.
The
amazing
results
from
the
pluto
and
the
936
61..
We
want
to
duplicate
that
for
the
9371
on
the
zc706,
and
we
also
want
to
carry
that
forward
onto
the
ultrascale,
and
I
haven't
even
started
looking
at
the
zcu
106
or
any
of
the
ultrascale
devices.
A
B
Okay,
I
just
I'm
just
trying
to
analyze
the
the
pdf
on
the
design.
So
right
now
the
dvbs
tune.
Color
is
only
connected
on
the
sx
lights.
There
is
no
input,
neither
output
of
data's
right.
A
B
A
C
A
B
A
Because
I
tried
to
generate
the
system
block
diagram
to
show
how
it's
currently
hooked
up
and
it
turns
out
it's
not
right,
so
it
only
has
the
the
light
interface
hooked
up
in
the
export
that
I
did,
but
I'm
kind
of
concerned,
because
that
is
that's.
Oh
there
we
go.
Okay,
I
found
the
right.
A
A
Yes,
yeah.
No,
I
think
it's
got
to
be
something
simple
that
we're
doing.
Okay.
Here
we
go
all
right.
So
now
I'm
going
to
share
it.
Sorry
for
the
delay
here.
Okay,
first,
I
probably
need
to
open
it.
A
A
A
We
we
now
understand
what
it
does
and
the
default
hardware
reference
design
from
analog
devices
has
a
64-bit
read
from
ddr
memory
and
then
produces
a
128-bit
wide
stream
that
goes
off
the
dac,
fifo
and
then
goes
downstream,
and
what
it's,
assuming
that
it's
getting,
is
two
channels
for,
because
we
have
two
transmitters,
zero
and
one,
and
it
gets
32
bits
for
channel
one
and
then
30.
A
Oh
sorry,
32
bits
for
channel
zero,
32
bits
for
channel
one
16
bit
iq,
and
so
our
job
was
to
figure
out
how
to
do
the
correct
bus
sizing
and
then
fit
the
encoder
in
and
so
that
that's
how
we
chose
to
do
it
on
the
bottom.
So
we
dropped
the
encoder
in
between
the
transmit
dma
and
the
dac
fifo,
which
left
the
master.
Axi
stream
transfer
request
line
connected
from
the
transmit
dma
controller
off
to
the
dac
fifo,
because
I
wasn't
really
sure
what
else
to
do
with
it
in
the
pluto
design.
A
This
is
not
connected,
the
signal
doesn't
exist
or
the
signal
exists.
The
the
pins
exist,
but
it's
not
connected
in
the
pluto,
probably
because
there
isn't
a
dac
fifo.
The
dvb
encoder
connects
directly
up
to
rrc
interpolator,
so
we
dropped
the
dbb
encoder
in
here,
and
this
is
the
connections
and
then
the
this
particular
bit
file
was
exported
and
this
xa
xsa
is
what
we're
using
and
now.
I
have
no
idea
why
the
exported
board
system
board
diagram
doesn't
show
this
and
so
I'll.
Maybe
that's
the
problem.
A
I
don't
know,
but
in
any
case
the
problem
that
we're
having
doesn't
have
anything
to
do
with
any
of
the
stream
connections.
That
has
everything
to
do
with
the
light
x
or
light
connection.
The
axi
light
connection
is
from
the
processor
to
the
encoder,
and
that
is
that's
set
up
for
sure
in
the
tackle
script
in
the
board
treckle
script,
so
we
should
be
able
to
talk
to
the
encoder
from
the
processor
side,
just
like
anything
else,
with
any
sort
of
other
axi
interface.
A
We're
able
to
talk
to
the
dx
to
the
transmit,
dma
controller,
no
problem.
We
can
write
and
read
from
it
no
reads
or
writes
for
the
dvd
encoder
are
working
from
from
essentially
from
the
processor
side
right
now,
so
we've
done
something
probably
stupid
or
silly
or
you
know
it
is
in
the
device
tree.
B
So,
no
you,
you
don't
need
to
have
this
device
3
on
that,
as
there
is
no
kernel
module
right
as
you
will
access
it
directly
via
dev
member
okay,.
A
So
that's
that's!
That's
what
we're
using
so
devmem
shows
nothing
and
memory
map,
so
the
memory
map
actually
seems
to
succeed,
but
then,
when
you,
when
you
actually
use
the
memory
map
in
c
with
the
little
very
simple
c
program,
it
gives
the
bus
error.
B
A
B
B
A
B
A
B
Or
is
it
what
you
have
exported
without
any.
A
B
B
B
B
Yeah
when
I
used
on
the
pluto
bead
route,
and
the
problem
is
that
the
the
design
is
is
done
from
the
tickle
and
not
from
the
designer.
Well,
if
you,
if
you
modify
the
design
on
vivado,.
B
If
you
rebuild
all,
then
it
use
the
ttcl
of
of
the
project.
So
so
you
need.
B
Well,
when
you
you
draw
lines,
and
if
you
you
have
already
a
firmware
and
you
upload
the
bit
stream.
B
Directly
well
on
live
on
the
well
on
the
firmware.
You
you
use
the
tickle
okay
and
you
can
you
can
upload
some
new
bit
stream
on
live,
but
as
soon
as
you
remake
all
that
it
use
the
tickle
so
not.
C
A
C
A
Because
that's
in
the
tackle
the
that
connection,
the
light,
the
axa
light,
the
and
one
clock
and
and
one
reset-
and
we
see
that
like
when
you
make
this
and
you
call
it
up
in
vivato-
all
of
that
is
magically
there.
And
then
I
drew
the
rest
of
them.
But
it
didn't
take
because
it
goes
back
to
the
the
board
tackle.
A
B
Yeah,
just
I
just
explain
my
mistake
first,
is
I
well
how
I
work,
but
it's
not
it's
not.
Maybe
the
best
way
that.
B
And
then
I
I
I
put
make
then
I
have
an
xpr.
I
I
open
it
on
vivaldo
and
be
sure
that
all
the
connection
I
did
on
antiqual
is
okay.
If
not,
if
there
is
some
missing
lines,
then
I
plugged
this
missing
line,
see
how
the
tickle
is
well.
What
what
is
the
line
to
to
modify
well
on
vivado?
When
you
put
the
line,
then
you
have
some
typical
truss?
B
Well,
some
script.
I
can't
remember
you
have
a
t
called
console.
A
B
And
then
it
helps
to
to
write
the
tickle
script
so
when,
when
there
are
some
missing
lines,
I
usually
copy
the
what
what
I
what
I
write
in
design
well
with
vivado,
I
I
I
copy
it
to
the
tickle.
A
C
B
B
It
is
not
scrambled,
but
it's
not
very
easy
to
read.
So
usually
I
try
to
make
the
tickle
by
you
by
hand
gotcha.
A
B
A
C
C
A
A
A
B
The
the
other
idea-
I
don't
know
if
how
did
you
choose
the
the
address
of
the
dvd.
A
This
was,
does
anybody
know
where
the
address
came
from
paul?
Do
you
remember
it's
always
been
44
abe
8000
it
was
that
was
in
the
vivado
that
was
in
the
hdl.
It
was
in.
B
A
A
C
A
C
B
Yeah,
the
only
okay
another
thing,
so
I
think
it's
maybe
a
question
to
tutor,
but
I
use
right
now:
the
there
is
several
version
of
the
f
of
the
in
caller.
A
B
All
the
modifications
which
have
been
done
with
the
pluto
sdr
trial
that
could
be
also.
B
B
C
C
A
C
A
C
A
Scratch
register
and
everything
it
works
fine,
but
like
every,
we
get
a
bus
error
every
time
for
our
own
ip,
but
we
have
this
axi
light
interface
and
I'm
pretty
sure
that
that's
the
interface
that
communicates
to
the
control
registers
and
config
registers.
So
we've
done
so
we've
done
something
wrong
like
in
maybe
in
pedal,
linux
or
x.
Exporting
maybe
I
mean,
but
I
can't
find
anything.
A
C
B
What
I
don't
know
if,
if
well
as
there
is
no
data
stream
input
on
output,
I
don't
know
if
even
you
you
you
you
normally
theoretically
can
read
the
regis.
I
don't
know
if
the
decline
of
the
db
of
being
caller.
A
B
Could
try
also
on
the
on
the
pluto
side,
to
remove
the
the
stream
datas
and
try
to
read
the
register?
But
that's.
B
A
C
A
Even
though
I
thought
we
had
hooked
it
up
because
I
hooked
it
up
in
laboriously
hooked
it
up
in
the
in
the
in
the
schematic
and
then
I
but
then
I
exported
the
bitstream
and
if
it
rebuilds,
if
avatar
calls
all
those
jekyll
scripts,
then
it
just
overwrites
what
I've
done.
C
A
What
you
have
in
that
board
tackle
so
if
we
just
go
back
and
put
our
new
connections
into
the
tekl
script,
and
maybe
at
the
same
time
just
let
let
we
could
just
go
ahead
and
put
in
the
additional
files
that
are
missing,
and
then
that
means
that
your
repository
does
it
all
and
then
so
it's
all
summarized
in
the
issue
on
your
repository,
and
I
mean
I
can
try
to
do
it.
A
I
just
don't
know
how
to
I
don't
know
how
to
to
get
the
files
to
show
up,
but
I
think
I
can
probably
edit
the
the
hard-coded
directory
things
and
we
can
and
now
we
know
the
connections
that
we
need
to
do
from
the
diagram.
So
if
we
add
the
board
connections
into
that
particular
tucle
script
and
then
redo
all
of
this,
if
we
still
get
the
same
problem,
then
it's
some
other
problem.
C
C
A
C
C
So
bef
just
want
to
express
that
instead
of
that,
can
I
make
this
new
tackle
script
based
on
the
connections
that
we
have
made
yeah
test
it
out,
and
then
I
can
improve
all
on
the
changes
that
we
have
that
we
are
talking
on
the
slack.
That
way,
we
will
be
sure
that,
because
we
both
are
at
the
same
page,
we
have
our
connections
and
everything
repository
is
building.
C
I
will
try
to
get
a
new
tackle
script,
see
if
the
error
goes
and
then
I
will
improve
on
all
the
hard-coded
path
and
everything.
C
B
Yeah
I
can,
I
can
try
to
any
help.
B
If
there
is
a
big
mistake,
but
I
think
that
your
plan
is
okay
to
yes
to
write
article,
which
is
complete
and
try
to
have
well,
for
example,
a
design
that
I
can
clone
easily.
B
It
could
help
also
other
person
to
replate
replicate
that's
what
I
try
to
do
with
the
pluto.
I
think
that
it's
working,
so
maybe
you
can
you
can
inspire
of
how
I
I
did
it.
Maybe
it's
not
that
way,
but
I
think
that's
the
the
firmware
is
complete,
even
with
hdl
and
all
the
yes
all
the
stuff
so
yeah.
I
think
that
tickle
could
be
a
good
idea
as
soon
as
you
put
your
firmware
and
I
yeah
I
I
can.
I
can
review
on
your
pc
remotely.
A
Awesome,
thank
you.
Okay.
Is
there
any
any
opinions
about
the
the
master,
xi
stream
x,
f,
e
r
request
line
that
comes
from
d
from
tx
dma
and
it
goes
off
to
the
dac
fifo.
This
is
not
connected
up
in
the
pluto
design,
but
it,
but
we
have
it.
I've
left
it
in
place,
but
I'm
concerned
that
this
signal
is
going
to
screw
us
up.
Does
anybody
know
anything
about
it?
C
A
A
You
see
it
like,
it
was
it's
in
the
design
and
it's
in
the
little
diagram
like
I
wasn't
sure
what
to
do
with
it.
So
I
kept
it
connected
from
the
from
the
dma
up
to
the
dak
fifo.
A
A
This
do
and,
and
it
turns
out,
it
goes
high
when
there's
a
dma
request
and
it
stays
high
as
long
as
there's
gma
requests,
but
now
that
we
have
logic
in
the
middle,
I'm
worried
that
it'll
it'll
de-assert
before
we're
done
with
the
the
encoder,
and
you
don't
have
the
signal
hooked
up
at
all
in
the
pluto
and
it
seems
to
work
just
fine
so
like,
but
you
go
from
dma
to
encoder
to
the
rrc
interpolator.
You
don't
go
through
a
fifo
for
dac.
B
A
A
It
looked
important
and
I
don't
know
what
to
do
with
it
or
if
we
have
to
manipulate
the
signal
or
incorporate
it
in
any
way,
I'd
like
to
use
it
if
we
have
to
so
I
it's
not
responsible.
The
signal
is
not
responsible
for
the
problems
we're
currently
having,
but
I
I'm
looking
forward
a
couple
of
days
from
now.
You
know
when
we're
triumphant
and
victorious
and
everything
was
working
and
then
we
go.
Why
is
it
cutting
off
our
transmission
too
early?
A
Then
you
know
if
we
have
to
take
care
of
this,
then
at
least
we'll
know.
So
that's
the
only
signal
that
I
wasn't
really
sure
about
how
to
connect
up.
C
A
A
Yeah:
okay,
let's
just
plan
on
that,
I'm
not
so
I'll.
Keep
it
hooked
up
the
way.
It
is
right
now
you
know
but
like
like,
I
don't
want
to
say
that
every
design
works
just
fine.
C
A
Without
this
signal
at
all,
so
you
know
it's
it,
it
might
not
be
optional
for
us,
but
I
don't
know
yet
and
it's
so
if
you
feel
confident
enough
to
go
plow
through
hdl
source
code,
you
can
see
where
it
is.
A
I
think
I've
cut
and
pasted
some
some
notes
just
slack,
but
yeah.
That's
just
something.
This
is
one
of
the
things
I'm
trying
to
track
and
worry
about
cool.
Okay,
I
think
we
have
a
plan.
This
is
great,
so
yeah,
if
you,
if
you
need
to
drop
off
the
call
from
from
here
fine.
So
so
what
I'd
like
to
talk
about
next
is
remote
lab
south
fpga
stations
and
development
and
capital
expenses
and
planning
for
for
the
for
that
particular
lab
with
james.
A
So,
if
you're
interested
in
that,
please
stay
on
the
call
and,
if
not
then
have
a
wonderful
morning
or
evening
wherever
you
are,
and
we
will
be
posting
updates
for
our
next
set
of
action
items
and
experiments
as
soon
as
we
possibly
can.
Okay.
A
Yeah,
no
thank
you.
This
is
fantastic.
It's
a
privilege
to
work
with
all
of
you,
wonderful,
competent
people.
Thank
you
so
much
for
your
time
and
very
soon
we're
going
to
be
working
with
a
working
downlink
and
then
we'll
have
to
work
on
the
scheduler,
which
is
how
do
we
feed
it
and
what
quality
of
service
decisions
do
we
make,
and
all
of
that?
Wonderful,
adaptive,
coding
and
modulation
magic
will
happen
and
it
will
be
just
as
hard
and
there
will
be
all
sorts
of
problems
to
happen
there.
A
Oh,
I
should
probably
say
before
you
go,
that
we
do
have
vitas
working
on
the
zc706,
so
the
problem
that
we
have
with
choco
cat
and
probably
with
karapi
as
well,
is
that
when
you're
in
vitus,
if
you're
going
to
use
vitus
the
ide
from
from
xylinx
for
the
processor
side
that
the
when
you
go
to
create
project
platform
which
is
required
before
you
get
to
your
application,
programming
and
you'll
notice
that
if
you
use
the
drop
down
menu
and
click
on
it,
nothing
happens.
A
It's
known
there
are
dozens
of
people
complaining
about
it
on
the
web
and
there's
a
workaround.
So
instead
of
using
the
graphical
user
interface,
you
have
to
use
the
command
line,
which
is
platform
create
and
then
a
whole
bunch
of
stuff
that
you
have
to.
So
what
I'm
going
to
do
is
add
it
to
our
repository
readme
for
how
to
use
fpgas.
A
C
A
Creating
an
application-
and
so
thank
you
to
engineer
zone
stack
overflow,
google,
for
google
search
for
for
all
the
different
items,
so
you
can
get
through
with
a
with
a
command
line
thing
and
it.
It
just
goes
to
show
you
that
big
companies
with
their
proprietary
tools
have
bad
bugs
that
you
know
we
can't
help
books
and
you
know
it's
it's
it's
just
a
a
note.
A
So
what
I'll
do
is
I'll
make
sure
that
that
is
in
the
that's
in
our
documentation,
so
that
you're,
not
flummoxed
or
or
sidelined
by
that,
because
and
oh
if
you
do
go
straight
to
the
create
application
first,
which
is
what
I
did
the
other
day.
Thinking
that
you
just
have
to
create
an
application
on
the
processor
side,
if
you
don't
do
the
project
platform,
first
you'll
crash
the
zc706
and
it
will
be
bricked
for
some.
B
A
So
that's
what
happened!
Anshul
when
you
said
that
you
couldn't
find
the
target.
It's
because
I
tried
to
run
an
application
and
it
just
crashed,
and
I
didn't
understand
why
and
didn't
think
of
it.
So
I
repeated
it
after
you
talked
to
me
and
sure
enough:
you
can.
You
can
completely
brick
the
zc706
by
going
straight
to
application.
So
all
of
this
all
I'll
make
sure
it's
written
down
just
a
little
just
yet
another
learning
opportunity
for
us.
You
know,
but
once
you.
C
A
Platform
creation,
if
you
just
do
the
whole
thing,
then
you're
all
of
a
sudden
you're
in
a
debugger,
and
you
got
you
got
access
to
the
cc706
and
that's
what
we'll
probably
be
using
to
write
the
scheduler
and
all
of
the
multiplexing
software
to
connect
the
uplink
and
downlink.
So,
okay.
So
anyway,
that's
the
that's
the
big
win
for
this
week.
It
was
a
lot
of
work,
but
we're
pretty
confident.
That's
the
way
to
do
it
and
yeah
see
you
on
slack
and
and
next
week
same
time,.
C
Sure,
and
just
one
last
one
this
right
is:
did
you
install
it
on
ps
side
or
it's
on
the
host?
That's
connected
to
the
sync.
A
All
in
the
host,
it's
all
cross
compilation,
it's
all
it
all
magically
works
because
you've
included
the
xsa
file.
You've
incorporated
all
of
the
what
you
need
to
know
so
you're
not
having
to
write
code
on
the
host.
Now
you
can,
if
you
want
to,
but
you
have
to
go
back
to
pedal
linux
and
include
a
c
environment
and
then
in
pedal
linux
and
then
reboot.
It.
B
C
C
A
C
A
It's
essentially
the
sdk
for
for
so
it
runs
all
on
choco
cat
and
then
and
then,
when
you
run
the
debugger,
if
you
set
it
up,
you
know
with
the
with
a
couple
of
steps,
then
you
set
it
up.
Then
it's
deploying
the
elf
file
directly
to
the
the
zc706.
C
These
are
plus
and
right,
apart
from
mentioning
the
steps
in
the
readme,
have
you
pasted
it
on
the
slack
also.
A
I
think
so
not
no!
I
did
not
do.
A
C
A
C
A
About
did
not
show
up
in
the
debugger
it
just
just
it
just
halts,
it
just
stops,
and
it
doesn't
give
you
the
same
error.
C
C
C
A
There
is
a
way
to
show
it.
I
haven't
found
it
out
yet
so
I
apologize
to
anybody
out
there
listening
to
this.
That's
a
big
fan
of
vitus
and
knows
how
to
do
this.
If
you
have
advice
for
us,
we
would
like
to
hear
it.
You
know,
so
let
us
know
where
we're
on,
but
it
it
just
stops.
It
just
halts
so
and
you
have
to
kind
of
figure
it
out
from
looking
at
the
registers,
which
you.
C
C
A
C
A
All
right,
james
thanks
so
much
for
hanging
in
there.
Hey
tell
us,
I
know
it's,
it's
probably
hot
there
and
have
you
had
any
thunderstorms
and
we
are.
We
have
funding
lined
up
and
I
think
we're
just
waiting
for
documentation
for
just
to
make
it
really
clean
and
easy
for
the
501c3
to
fund
the
lab
work.
C
That
is,
that
is
all
correct.
It's
been
pretty
hot
here,
but
you
have
the
advantage
of
architecture
and
air
conditioning
all
built
for
this
kind
of
weather.
So
it's
been
pretty
good
until
the
dog
goes,
but
it's
been
15
minutes
since
I
went
outside
so
now.
I
must
go
outside
for
the
next
half
hour
like
dog,
please
no
yeah.
C
A
C
A
Though,
because
now
I
live
in
california
and
it's
a
mediterranean
climate
here,
so
not
to
rub
it
in
or
anything
but
yeah
it's
so
the
funding
is
lined
up
for
all
of
the
modifications
and
I
think
yeah
I
think
we're
just
we
just.
I
know
that
this
week
is
when
the
paperwork
will
get
delivered.
C
A
Done
and
it
should
be
an
easy
discussion
at
the
board
level
for
ori
to
to
fund
it
and
get
it
to
happen,
and
then
the
hard
part
is
is
kind
of.
A
I
think
if,
if
we're,
if
we're
wanting
to
include
universities
and
students,
what
we
found
is
is
all
the
things
that
that
you
and
all
of
your
people
there
already
know,
and
that
is
that
working
with
universities
requires
some
some
patience
and
some
persistence
and
some
consistency
and
it
has
to
fit
in
with
their
particular
pedagogy
and
student
plans
and
blah
blah
blah.
A
So
if
you
want
to
tackle
universities,
you
should
because
that's
one
of
the
missions
that
we
have
you
know,
but
like
independent
researchers
and
hobbyists
and
enthusiasts,
and
and
also
people
that
want
to
use
this
opportunity
to
work
on
open
source
software
in
order
to
like
build
up
a
better
career.
We
are
all
in
on
that
too,
but
the
outreach
and-
and
you
know,
communications
required
to
to
talk
to
people
that
are
interested
in
that
is
is,
is,
can
be
very
time
consuming.
A
C
A
Yeah,
I
I
so
I'm
here
to
help
and
just
don't
give
up
it's
a
it's
a.
It
requires
an
awful
lot
of
repetitive
iterative
outreach
in
order
to
to
make
the
the
resource
known
and
then
there,
as
you
can
see
from
today's
discussion,
there's
a
steep
learning
curve
at
every
step
in
almost
every
direction.
A
So
so
it's
you
know
it's
just
you
approach
it
with
some
joy
and
enthusiasm,
and
I
think
I
think
you've
already
got
those
things
down
and
and
you're
you're,
already
well-versed
and
and
competent
in
that
yeah,
so
yeah.
I
think
we're
going
to
be
able
to
build
not
just
a
fpga
sort
of
nexus.
Another
a
station
very
similar
to
what
we
have
already
in
the
uk
and
in
san
diego,
but
the
the
remote
labs
south
also
has
a
biomedical
lab
planned
as
well.
A
So
that's
a
completely
different
type
of
endeavor,
but
we're
we're
very
committed
to
seeing
that
happen
and
very
excited
about
it.
So
there's
been
some
discussion
about
the
physical
physical
plant
requirements
for
a
bio
for
a
bacteriophage
or
any
other
biological
or
or
agricultural
work,
and
that
brings
us
to
fundraising.
So
there
are
some
some
funds,
some
some
grants
that
we
are
targeting.
A
A
So
what
we
would
really
like
to
do
is
instead
of
nuking
the
poor
fish
with
more
and
more
antibiotics
for
all
of
the
different
bacterial
infections
that
plague
fish
farms
and
there's
a
growing
problem
there
that,
instead
of
using
you
know
this
arms
race
with
antibiotics,
that
we
try
a
cocktail
of
bacteriophage
and
kind
of
the
benefit
of
doing
this
is
that
that
fish
are
cheaper
to
work
with
than
humans.
A
And
it's
at
least
several
million
just
to
get
off
the
ground
with
a
team
of
three
people
doing
the
work.
So
we
don't
have
a
million
dollars
for
that,
but
we
do
have
enough
money
to
to
tackle
a
problem
that
is
arguably
just
as
pressing
and
that
is
feeding
people
and
feeding
vulnerable
people.
So
fish
farms
around
the
world
can
really
feed
a
lot
of
people.
A
So
back
you
know,
looking
at
the
problems
of
fish
farms
and
and
whether
or
not
a
bacteriophage
cocktail
can
work,
we
can
actually
set
up
an
aquaponics
greenhouse
or
you
know,
a
very
small
commercial
style
fish
farm,
especially
in
arkansas.
I
think
that
the
climate
is
really
well
suited
to
this
and
there's
already
existing
farms
that
we
might
be
able
to
collaborate
with
and
uams
might
be
interested
in
this,
and
we
do
have
a
bacteriophage.
A
Initiative
or
institute
here
at
ucsd
at
the
university
of
california
at
san
diego,
they
went
on
hiatus
with
kovid
and
have
not
really
come
out
of
it
yet,
but
they
know
about
us
and
any
day
we're
hoping
that
it
becomes
a
little
more
active.
So
so
anyway,
that's
one
of
the
things
that
that
we
are
interested
in
in
seeing
if
it
can
happen
at
remote
love
south,
is
to
also
add,
essentially
a
wet
lab
for
bacteriophage
work.
A
C
Very
excited
to
begin
work
on
that
project
and
to
expand
our
eyes
different
methods
and
different
fields
of
research.
Even
further.
A
Yeah,
I'm
excited
about
it,
the
there's
at
least
two
fda
grants
that
are
open
right
now
and
we
don't
have
to
to
leap
for
these.
It's
just
proof
that
we're
on
the
right
track.
There's
there's
one
on
innovative
farming
that
might
help
fund
some
work
to
get
to
kickstart,
the
bacteriophage
for
for
fish
farms,
but
there's
another
one.
That's
these
are.
A
These
are
grants
that
happen
fairly
routinely
but
for
a
grant
available
for
a
workshop
or
conference,
and
so
I'd
like
to
to
propose
that
we
really
seriously
think
about
either
a
workshop
or
a
small
conference
either
in
little
rock
or
somewhere
else.
I
think
little
rock
would
work
for
for
gathering
together
scientists
and
and
engineers
that
want
to
work
on
this.
So
if
we
have
a
focused
sort
of
sort
of
scientific
conference
or
scientific
workshop,
there
there's
money
available
through
right.
A
It
looks
like
either
department
of
agriculture,
fda
or
or
nsf,
so
as
soon
as
possible.
What
I'll
do
is
I'll?
Send
you
the
proposal
or
the
request
for
for
proposals
for
the
the
conference
and
see
what
you
think
and
if
we
can't
hit
this
one
by
the
deadline,
then
we
should
look
for
the
next
one
and
and
try
to
start
putting
together
a
conference
or
workshop.
It
does
not
have
to
be
large
to
be
effective,
but
I
think
we
could
could
make
a
good
yeah.
A
A
Okay,
well
today,
I
will
send
you
the
the
details
on
those
two
requests,
their
solicitations
for
for
grants
and
then
we'll
we'll
see
what
we
can
do
to
try
to
to
put
together
a
decent
proposal.
It'll
probably
take
at
least
the
in
order
to
really
do
this
right,
we'll
need
to
have
some
some
regular
meetings
in
the
short
term
to
to
hammer
it
out
and
I'll
help.
All
that
I
can
so
that'll
be
something
that'll
I'll
turn
around
to
you
guys
today.
A
A
Thank
you
all
right,
paul
anything
from
you.
C
Hanging
out
with
some
of
this
stuff,
but
everything
is
situation
normal
in
the
west
lab.
A
Thank
you.
Thank
you
very
much.
Your
your
expertise
and
and
and
all
of
your
help
is
deeply
appreciated.
Could
not
we
would
not
be
here
without
you
any
any
thoughts
on
the
uplink
or
work
there.
That
needs
to
be
so
like.
I
did.
I
think
we're
probably
gonna
have
to
start
talking
about
what
is
receiving
the
uplink
on
the
on
the
fpga
side.
So
the
we've
talked
about
polyphase
analyzers
and
it's
been
a
while,
since
we
demonstrated
the
poly
phase,
filter
bank
stuff,
any
thoughts
there
or
too
early.
A
All
right,
I'm
thinking
about
it,
but
I
I
think
we're
in
decent
shape.
I
know
that
the
thesis
course
will
have
to
be
modified
because
it
targets
the
70
45
instead
of
what
we've
got,
but
the
code's
good.
There
is
a
known
bug
with
the
number
of
channels,
so
the
implementation.
The
last
time
I
talked
to
the
thesis
course
people
this
will
for
those
of
you
listening.
This
is
what
receives
the
uplink.
A
It's
a
frequency
division,
multiple
access,
uplink
and
it
needs
to
be
received
that
way
and
then
digitized
or
decoded,
demodulated,
decoded
and
then
multiplexed.
But
you
know
you
first,
you
have
to
receive
it
and
we
believe
that
the
best
way
to
do
that
is
with
the
polyface
channelizer
and
we
do
have
a
solid,
open
source
base
to
work
from,
but
it's
going
to
have
to
be
ported
to
our
our
system
and
there's
an
interesting
bug.
A
So
we
should
be
aware
that
there
might
be
a
raw
channel
limit
that
we
need
to
address
and
it
might
require
some
backing
up
and
looking
at
what
happened
so
it
could
have
already
been
fixed,
but
I
that
was
the
it
was
a
very
interesting
and
somewhat
subtle
thing
that
really
kind
of
wrecked
anything
above
eight
channels,
and
we
will
definitely
be
requiring
more
than
eight
channels.
So
that's
all
I
know
about
that.
So
it's
that's
well
well,
past.
A
A
Okay,
thank
you,
everybody!
Thank
you
for
everybody.
That's
that's!
Listening
for
your
support
and
positive
vibes.
It
makes
all
the
difference
in
the
world
and
we're
looking
forward
to
being
able
to
share
videos
of
things
working
and
it's
a
delightful
project
to
work
on,
and
we
hope
that
it
brings
a
lot
of
joy
to
people
that
use
it
all
right,
see
you
on
slack.