►
From YouTube: ORI FPGA Office Hours
Description
MATLAB Course Proposal
Remote Lab Reports
A
A
Hello,
everybody
here's
the
course
proposal,
because
you
are
invited
to
the
open,
Research,
Institute,
Matlab
and
fpga
training.
This
is
proposed
for
May
2023
on
the
internet
and
we
need
your
feedback.
So
here's
the
The
Proposal
after
an
amount
of
work
between
math
works
and
and
open
Research
Institute
on
on
what
we
think
our
volunteers
might
need
in
order
to
step
forward
and
produce
some
and
Implement
some
some
of
our
designs
that
we've
been
looking
at
and
to
better
support
the
open
source
community.
A
So
the
course
proposal
it's
a.
This
is
over
four
days
total,
but
you'll
see
three
days
listed
the
third
day
since
it's
Hardware
Centric
is
split
over
two
days
day.
One
is
preparing
simulink
models
for
HDL
or
Hardware,
descriptive
language
code
generation,
and
it's
kind
of
the
heart
of
what
we're
after
is
to
get
to
HDL
and
fpga
implementations
through
Matlab
and
simulink
as
quickly
as
possible.
A
There's
a
toolbox
called
HDL
coder,
and
that
is
the
focus
of
this
particular
training:
how
to
use
it,
how
to
prepare
your
models
and
your
Matlab
Scripts
for
for
the
best
possible
outcome
from
HDL
coder
and
so
on
day.
One
we
start
off
with
preparing
a
simulink
model
for
HDL
code
generation,
we're
going
to
generate
the
HDL
code,
and
this
is
human
readable
in
my
experiences
so
far,
the
the
quality
of
the
HDL
code,
that's
produced
by
HDL
coder
toolbox
is
excellent
and
it
also
can
produce
a
test
bench
at
the
same
time.
A
A
Move
on
to
fixed
Point,
Precision
control,
this
establishes
a
correspondence
between
the
generated
HDL
code
and
that
specific
simulink
blocks
that
you
used
in
your
model,
and
this
is
using
the
fixed
Point
tool
to
finalize
the
fixed
Point
architecture
of
the
model.
So
this
is
scaling
and
inheritance
and
designer
workflow
and
all
of
the
things
that
you
see
here
so
that's
estimated
to
take
about
two
hours
now.
This
is
one
of
those
things
that
our
particular
Community
might
not
need
to
spend
the
entire
two
hours
on
so
I'd.
A
A
This
is
where
we
use
specific
Hardware
implementations
and
we're
looking
at
all
the
different
optimizations
that
are
available
to
us,
including
area,
so
that's
kind
of
like
the
meat
of
the
the
second
part
of
day,
one
after
you've
digested
all
of
that
day.
Two
is
signal
flow
graph
or
SVG
techniques
and
high
speed.
This
is
finite
input
impulse
response,
our
fir
filter
design.
A
So
we're
going
to
go
over
representation
of
DSP
algorithms
using
a
signal
flow
graph,
using
the
cut
set
method
to
improve
timing,
performance
and
Implement
parallel
and
serial
fir
filters.
Okay,
so
lots
and
lots
of
filters.
You
can
see
some
of
the
stuff
if
you've
never
done.
Filter
design
is
going
to
be
very
familiar
and
using
pipelining
and
multi-channel
architectures
in
the
topology.
That's
kind
of
like
sort
of
a
bread
and
butter
thing
in
in
simulink,
and
then
this
last
thing
is
important.
So
what
fir?
Filter
structures
are
most
appropriate
for
fpgas.
A
We
continue
on
with
something
that
we
are
are
very
interested
in
multi-rate
Signal
processing
for
fpgas.
This
is
four
hours.
This
is
polyphase
filter
techniques
and
polyfast
structures
and
multi-rate
filter
design.
So
up
sampling,
interpolation
filters
down,
sampling
and
decimation
filters,
the
arithmetic
involved,
integrators,
differentiators,
half
band
moving
average
comb
filters
and
the
Cascade
integrator
comb
filter
and
then
efficient
arithmetic
for
for
I
irr
filtering,
that's
a
lot
we
also
have
this
in.
Here
is
the
Cordic
techniques
and
channelizers,
and
this
is
cortic
algorithms.
A
This
is
primarily
addressing
trigonometric
trig
functions,
trigonometric
functions,
there's
rotations
and
vectors.
Cosines
and
Sines,
a
lot
of
us
may
already
be
familiar
with
this,
so
I'd
really
like
feedback.
If
you
want
to
spend
two
hours
on
this
to
go
over
it,
you
know,
or
if
there's
somebody
out
there
is
like
wow
I
would
totally
take
this
class
because
it
has
this
I
need
to
hear
from
from
both
of
you,
so
that
we
can
have
the
best
possible
weighing
and
considering
of
this
particular
course
outline
all
right
day.
A
So
the
first
thing
to
kind
of
address
is
like
exactly
how
you
deploy
the
IP
cores,
we're
relatively
familiar
with
this
as
a
as
a
community.
We've
been
able
to
to
accomplish
this,
but
there
is
in
this
particular
toolbox
from
HDL
coder.
The
way
that
you
accomplish
the
work
is
through
the
workflow
advisor
and
this
class
will
help
you
how
to
configure
your
simulink
model,
how
to
generate
and
build
the
HDL
and
C
code
deployed
to
a
zinc
platform
zinc
in
particular
from
silinks,
which
is
what
we're
using
in
remote
labs.
A
You
can
see
from
the
bullet
points,
there's
a
lot
of
stuff
going
on
here.
How
do
you
configure
your
sub
subsystems
for
the
programmable
logic
fabric?
How
do
you
target
the
interface?
How
do
you
handle
peripherals,
generating
the
IP
core
and
integrating
with
the
SDK
I
think
we
we
got
this.
This
is
the
IP
publishing
or
IP
generation
packaging
process
and
there's
a
a
pretty
a
pretty
good
process
or
workflow
from
vivato.
A
We've
had
relatively
little
difficulty
using
it,
but
then
building
and
deploying
your
fpga
bit
stream.
How
do
you
get
the
software
interface
model
and
then
how
do
you
tune
parameters
from
the
outside?
So
some
of
this
we
have
had
trouble
with
figuring
out
how
to
get
the
the
general
purpose
processing
part
or
the
the
application
processor
to
properly
communicate
with
and
handle
the
bitstream.
A
One
of
the
problems
that
we've
had
is
with
the
buffer
timeouts
on
the
transmitter
so
day
three
continues
and
it's
called
Model
communication
system
using
simulink.
So
what
this
is
is
looking
at
the
80
9361.
This
is
the
the
chip.
That's
on
the
Pluto.
You
know
just
in
particular
this
this
number
here.
A
If
you
see
the
9361,
that
means
the
the
analog
device
is
Pluto
and
this
is
to
model
and
understand
a
transceiver
using
simulink,
so
you're
going
to
simulate
a
communication
system
that
includes
a
transmitter,
transceiver,
Channel
and
receiver,
and
implement
the
radio
I
o,
and
so,
if
you've
played
around
with
the
Pluto
within
an
fpga
context.
A
lot
of
this
is
going
to
be
very
familiar
and
like
yeah
yeah,
that's
that's
right.
The
this
particular
training
approaches
it
from
a
Matlab
and
simulink
perspective.
A
So
we
are
interested
in
verification
of
validation
here
in
this
class,
is,
is
going
to
get
at
some
of
the
tools
to
let
you
do
that
in
a
formal
way.
They're
system
objects.
That's
a
thing
in
Matlab
having
these
various
system
objects,
you
make
the
system
object.
Then
you
call
the
system
object,
almost
like
a
function
and
we've
used
these
for
the
modulators
demodulators
forward,
error,
correction
and
other
things
so
being
able
to
use
these
and
get
them
into
a
bit
stream.
That
sounds
exciting
to
me.
A
So
you
can
see
that
the
rest
like,
including
like
configuring,
the
registers
and
filters
with
the
system,
object
and
verifying
real
versus
simulated
data,
something
that
Matlab
and
simulink
and
heavily
relies
upon
when
it
comes
to
sort
of
the
xilinx
and
and
Analog
Devices
world
is
libio,
which
is
what
we've
been
using
all
along.
We've
been
using
it
primarily
with
petal
Linux,
so
it
will
not
be
a
big
difference
here.
A
And
then
this
is
kind
of
interesting
tuning.
The
system
parameters
in
real-time
operation,
video
simulink,
that's
that's
cool!
So
what
we're
talking
about
here
is
sort
of
the
system
in
the
loop
or
fpga
in
the
loop,
where
okay
now
you're
going
to
make
sure
that
your
system
works.
The
way
you
intended
and
and
setting
up
a
big
outer
loop
to
test
these
things
and
then
finally,
letting
go
of
all
these
loops
and
deploying
a
standalone
system.
A
A
If
we
want
this
date,
if
we
think
this
is
great
for
us,
then
we
need
to
confirm
to
back
to
them
by
the
4th
of
April
pay
for
everybody
at
least
10
people
by
the
12th
of
April.
The
class
would
run
9
A.M
to
5
00
p.m.
With
seven
hours
of
content,
there's
breaks
worked
in
there
and
we
have
not
yet
talked
about
time
zone.
A
A
If
it's
okay,
if
we
have
enough
people
at
least
10
people,
then
we
can
proceed
to
go
ahead
and
offer
this
class.
So
what
are
the
costs?
This
is
five
thousand
dollars
per
day
for
up
to
10
attendees
and
it's
350
per
day
after
that
they
max
out
at
15.
That's
the
absolute
maximum,
but
since
this
is
has
some
hardware-centric
approach
and
it
has
you,
logging
in
more
than
12,
is
really
hard,
so
we're
looking
at
really
10
to
12.
A
all
right.
So
what
do
we
need?
We
need
students
if
you
want
to
learn
this
stuff.
You
want
to
learn
this
little
workflow.
You
want
to
help
Implement
these
complex,
open
source
designs
using
this
workflow.
Then
this
is
for
you.
If
you
wanted,
it
can
also
help
you
in
a
career
path.
You
can
say:
I
am
formally
trained
in
this.
A
It
will
improve
you
and
your
your
interests
in
your
career
and
your
engineering
vocation
in
many
ways,
but
if
you're
interested
in
taking
this
training,
please
get
in
touch,
even
if
the
dates
don't
work
out
for
you,
even
if
it's
like
wow,
you
know,
I
can't
afford
whatever
it
divides
out
to
be
per
person.
We
need
to
hear
from
you
because
we
need
to
know
if
this
is
something
that
people
are
interested
in
and
especially
if
you
think
this
is
way
too
advanced.
A
A
There's
never
been
a
better
time
to
do.
Radio
work
and
it's
with
cheap
Computing
and
cheap
gain
and
decreasing
prices
for
microwave
gear.
This
should
be
much
more
accessible
to
open
source,
amateur
radio,
digital
Communications
Folks
at
all
levels,
so
we're
here
to
help
with
this.
This
is
part
of
our
mission.
We
also
need
some
some
help
financially.
This
would
be
great
to
be
subsidized.
A
If
you
are,
if
you
could
subsidize
it,
if
you
can
pay
for
it
yourself
fully
great,
please
do
if
you
know
of
a
foundation
that
might
be
interested
in
in
helping
this
class
happen
if
you're
a
company-
and
you
would
like
this
training
for
your
employees-
we
are
here
to
coordinate
with
you
I'm,
going
to
try
to
spread
the
word
as
wide
as
I
can
but
knows
nothing
that
beats
Word
of
Mouth
from
all
the
people.
Listening
to
this.
A
So
if
this
class
looks
good,
then
let
us
know
and
help
people
attend
from
your
company
or
your
organization
in
order
to
get
in
touch
with
us
directly.
The
people
that
are,
you
know
trying
to
help
this
happen.
Then
you
can
write
us
an
email
at
hello
at
open
research,
dot,
Institute
and
that
will
that
will
be
fantastic,
we'd
love
to
hear
from
you
feedback
of
any
any
type.
A
B
Hello
Michelle,
remote
Lab
news
is
your
dog.
Is
the
only
one
thing
to
report
in
remote
lab,
which
is
that
our
new
radio
has
arrived
at
the
post
office
box?
We'll
probably
collect
that
today
and
let
me
get
it
set
up
over
the
next
few
days.
Be
able
to
use
the
ad9002.
Is
that
the
right
adrb
9002?
Is
that
the
right
number?
That's.
A
B
A
Oh
just
a
little
bit
little
update
James
is
was
not
able
to
join
us
today,
he's
the
lead
for
remote
lab
South,
so
he
has
other
things
that
he
had
to
do
today,
but
he
gives
a
big
thumbs
up
and
says
things
are
moving
forward
and
we
look
forward
to
to
having
some
some
photographs.
Video
pictures
from
the
physical
plant
development
at
remote,
lab
South
thank.
A
Well,
it
will
eventually
because
we'd
like
to
deploy
all
of
this
to
the
that,
essentially
the
the
transponder,
so
high
ferraria,
with
with
you
know
our
Geo
NGO
open
source
transponder.
This
will
be
the
receive
side
and
the
transmit
on
the
ground.
So
if
you,
if
you'd
like
to
talk
a
little
bit
about
that,
it'd
be
a
a
good
time
to
do
it.
B
This
means
increasing
the
sample
rate
in
order
to
accommodate
the
overhead,
and
that
means
changing
a
bunch
of
things
interleavers
and
filters
and
constants
that
are
here
and
there
in
the
code
trying
to
get
that
all
a
little
more
parameterized
than
it
was
before
and
working
again
at
the
higher
rate
and
the
first
attempt
did
not
work
at
all.
It
wouldn't
even
detect
the
data
carrier
reliably,
so
that's
been
fixed
and
moving
forward
to
the
next
thing,
which
is
something
that's
always
been
broken
in
the
demo
code.
B
B
This
is
not
rocket
science,
literally
or
figuratively,
but
does
require
a
fair
amount
of
chipping
away
at
and
especially
for
me,
I'm,
not
a
C,
plus
plus
expert,
so
the
C
plus
plus
stuff
is
somewhat
baffling
from
time
to
time.
That's
where
we
are
in
that
that's
progress
that
we
can
make.
Incrementally
start
to
see
some
waveforms
coming
out
and
maybe
even
hear
voices
coming
out
the
other
end
or
too
much
longer.
A
A
So
it's
a
big
step
forward
and
we
have
a
lot
of
confidence
in
that
particular
part
and
the
work
on
the
what
is
essentially
a
data
carrier
detect
was:
was
another
really
cool
learning
experience,
it's
like
it
all
it
all
sort
of
makes
sense.
So
it's
a
I'm
looking
forward
to
being
able
to
explain
the
the
improvements
and
and
the
the
sort
of
in
a
way
it's
sort
of
a
simplification,
because
this
particular
protocol
opulent
voices
both
simpler
and
more
complicated
than
a
lot
of
other
digital
digital
voice
systems.
A
They
are
they're,
adding
a
lot
of
overhead,
but
they
make
the
end
product
incredibly
useful
and
it
should
make
it
make
a
lot
of
the
stuff,
very
transparent
and
also
delivering
very
high
definition
voice.
So
you
know,
16
kilobits
per
second
is
quite
good,
as
you
demonstrated
in
your
ham.
Expo
talk
from
six
months
ago,
so
we'll
just
continue
to
do
this
and
the
the
team
working
on
it.
A
All
the
people
that
have
contributed
and
answered
questions-
and
you
know
and
in
your
efforts
are
very
appreciated,
it'll
whatever
we
have
will
be
demonstrated
in
August
at
Defcon
in
Las
Vegas.
Looking
forward
to
that
very
much,
and
you
know
if
you're,
if
you're
there,
please
join
us
in
RF
Village
all
right,
any
last
comments
or
or
anything
from
from
the
lab
that
you
need.
A
All
right,
cool,
well
I,
I,
look
forward
to
I'm
going
to
do
a
show
for
the
the
new
board
to
kind
of
highlight
the
differences
between
the
adrb
9002
and
the
edrv
9371,
and
to
point
out
the
differences
between
the
baseboard
to
bring
attention
to
the
resource
that
we
have
and
to
get
people.
You
know
if
you,
if
you
want
to
use
these
and
would
like
to
code
for
it,
then
we
have.
We
have
your
back,
so
that'll
be
coming
out
later
this
week.