►
From YouTube: 20220125 FPGA standup
Description
FPGA Stand-up meeting for 25 January 2022.
Progress on integrating custom IP with the ADVR9371.
A
All
right,
I'm
sharing
the
screen
I'll
go
ahead
and
start
so.
We've
had
a
step
forward
in
terms
of
using
remote
lab
or
making
it
more
usable,
because
that's
my
goal
here,
so
what
you
should
see
is
the
first
image.
This
is,
after
correctly,
building
the
dvds2
encoder
module
that
we've
written
and
that
took
some
doing
because
integrating
it
into
the
reference
design
from
analog
devices,
it
means
to
use
the
the
reference
design
sort
of
approach,
and
it
actually
is
very
similar
to
the
approach
that
you
would
do
for
a
standalone
module.
A
But
we,
you
have
to
kind
of
learn
how
to
how
to
modify
the
tekl
scripts
and
how
to
not
include
the
same
source
over
and
over
again
and
confuse
vivato.
So
that's
that
what
that
is
what
was
going
on
with
the
weird
failures
and
also
as
as
probably
the
rest
of
you
know,
you
can
wrap
the
the
whole
thing.
A
Well,
you
have
to
wrap.
You
have
to
use
wrapper
anyway,
that's
kind
of
the
way
that
we
do
it,
but
in
terms
of
like
presenting
the
correct
values
to
the
ports,
the
top
level
ports,
you
have
to
make
sure
that
you're
translating
any
non
standard
logic
or
standard
logic,
vector
values
correctly
to
the
top
level.
And
I
thought
that
that
just
happened,
but
no
it
doesn't.
You
actually
have
to
make
sure
that
it
happens,
especially
in
a
reference
design
like
what
we're
dealing
with
with
the
93
with
the
adrv
9371.
A
So
I'm
just
going
to
walk
through,
assuming
I
can
with
the
screen
sharing,
but
I'm
going
to
walk
through
this,
so
you
should
see
vivado
opened
to
the
reference
design,
there's
a
project
at
the
reference
design
and
then
oh
good,
okay.
So
what
I
do
here
is
just
open
the
design.
This
is,
after
the
correct
building
of
our
custom,
ip
module.
A
So
so
we've
built
our
encoder
into
the
reference
design
and
figured
out
all
the
bugs
and
then
got
it
to
work.
So
what
I
did
is
just
opened
up
the
the
block
diagram
for
the
reference
design.
You
can
see.
There's
lots
of
different
blocks
there
and
it's
it's
really
quite
a
good
design
takes
full
advantage
of
the
9371
board
and
then
I
say:
okay,
let's
add
a
module
and
look
at
that.
Our
module
actually
shows
up
in
the
list.
A
So
I
didn't
have
to
add
sources
or
anything
like
that,
because
the
ad
sources
is
taken
care
of
by
the
scripts
from
sawato
and
from
from
analog
devices.
So
after
getting
them
to
meet
in
the
middle
and
cooperate
together,
our
our
ip
module
shows
up
okay
and
then
what
I
did
is.
I
just
ran
the
connection
automation,
my
expectation
you
can
see.
There's
there's
like
a
this
little
block
here
that
didn't
exist
before
and
that's
our
that's
our
block.
So
I
just
ran
the
connection.
A
A
Now,
we've
already
run
some
data
all
the
way
through
the
reference
design
using
the
adi
api,
so
iio
or
industrial
input
output
interface
is,
is
really
the
best
bet
for
for
handling
the
chip
and
handling
shipping.
The
data
around
because
we're
using
the
9371
we're
using
jezd204b
interface
and
direct
memory
access
is
the
way
to
go
okay.
So
what
I
was
hoping
to
do
is
have
that
working
since
I'm
a
raging
optimist.
A
I
did
not
get
that
completely
working,
but
I
think
that
we're
really
close
to
using
our
encoder
over
the
air,
okay,
so
I'm
going
to
stop
sharing.
All
of
these
images
are
on
the
slack
in
the
fpga
channel
in
the
in
a
thread
and
I'll
include
them
in
the
weekly
report,
so
that
people
can
see
that
we
actually
did
get
our
our
particular
block
into
the
reference
design.
A
B
A
Yeah,
I
can
answer
that.
I
think
there
is
actually
a
way
to
make
it
do
that
there
there
may
be
a
way
to
make
it
do
that,
because
if
you
notice
the
rest
of
the
reference
design
does
go
ahead
and
automatically
hook
up
axi
interface,
but
the
the
walkthrough
from
analog
devices
does
warn
you
that
if
you
have
custom
ip
that
you're
bringing
in
that,
this
is
a
step
that
you
have
to
do.
So.
B
A
Fantastic,
I
can't
wait.
I
I
looked
at.
I
looked
through
the
slides
and
I'm
really
looking
forward
to
it
and
everybody
I
I
know
everybody
here
has
presented
at
ham
expo
before
and
it's
deeply
appreciated,
because
it's
a
huge
contribution
to
to
spread
the
word
and
to
to
let
people
know
what
we're
doing
so.
Thank
you.
A
A
A
Well,
I
don't
know
paul
has
informed
me
over
over
the
past
couple
of
years
that
laziness
is
a
cardinal
virtue
of
programming,
so
I
I
think
I
approve
of
laziness.
Yeah
just
grab
whatever
logs,
if
I
don't,
because
I'm
slow,
because
I
get
interrupted
a
lot
but
like
grab
whatever
logs
to
check
and
see
if
it's
going
the
way
that
you
expect,
because
I
did
not
get
any
errors
it
just
it
worked
as
expected,
which
was
kind
of
nice,
so
yeah.
A
A
Okay,
good
awesome,
all
right
so
yeah
step
forward
and
it's
yeah.
I
I
in
theory
like
it,
it's
really
quite
elegant
and
nice,
and
it's
a
big
step
forward
for
for
fpga
and
asic
design
to
use
jazz
d204b
and
but
now
I'm
like
okay,
so
I
just
hook
it
up
to
the
like.
I
just
connect
it
up
and
it's
gonna
magically
work
when
I
use
the
adi
api,
I'm
hoping
that
that
might
happen
and
that
I
see
stuff
on
the
spectrum
analyzer.
B
A
B
B
B
A
Thanks
yeah,
we
yeah-
I,
like
I
said
I'm
I
have
a.
I
have
a
background
in
making
asics
and
and
and
fpga
design,
but
it's
really
old
so
like
the
old-school
way
of
doing
things
is
very
different
from
this,
but
there's
a
lot
of
crossover,
but
it's
like
this
is
a
totally
huge
amazing
adventure.
I'm
loving
every
minute
of
it,
but
it
does
make
you
feel
stupid.
B
A
A
C
Oh
good,
I
thought
I
had
a
microphone
problem,
but
apparently
just
a
test
test
problem
not
too
much
to
report
here.
The
only
thing
going
on
with
the
remote
lab
is
that
we're
trying
to
reorganize
the
disk
space
usage-
everybody
except
salvatore-
has
cooperated
now
and
almost
ready
to
turn
off
the
vm
and
set
it
up
for
the
new
system,
which
I've
explained
to
everybody
in
the
slack
already.
A
A
You
know
which
is
which
is
fine
but
like
that
might
mean
like
a
two
day,
delay
worst
case
well.
Worst
case
is
going
to
be
like
a
week
if
we're
gone
but,
like
you
know,
there's
there's
two
people
here
that
know
how
to
do
that
and
a
third
is,
is
getting
trained.
So
obviously,
it'd
be
nice
for
the
linux
build
itself
to
not
have
the
bootloader
handle
the
the
bitstream.
A
Dr
jonathan,
black
from
virginia
tech,
wanted
me
to
stop
everything
and
write
it
all
down
so
that
he
could
take
it
and
publish
it
as
an
ieee
paper
because
he's
an
educator
and
is
now
on
sabbatical
in
the
uk
and
working
on
exactly
this
sort
of
problem,
and
he
says
that
nobody
really
attempts
to
do
this
at
the
level
that
we're
doing
so.
That's
good
and
bad
news.
A
It
shows
that
this
is
a
extremely
difficult
problem,
so
the
the
whole
thing
about
like
okay,
now
that
we
have
a
reference
design
that
can
go
to
a
bit
stream
yay.
How
do
you
then,
as
a
remote
user,
modify
this
and
then
get
it
working
with
the
build
of
linux?
That's
on
the
processor
side,
and
one
of
those
ways
is
to
have
linux
load.
D
A
Right
so
as
soon
as
we
do
that,
I
think
then
all
you
have
to
do.
All
you
have
to
do
is
to
your
bitstream
or
bin
file.
It
needs
to
be
a
bin
file.
It
can't
be
a
bit
file,
it
doesn't
need
the
header,
the
header
from
the
bit
file
confuses
things,
but
linux
just
wants
the
raw
like
just
the
data,
just
the
fax
ma'am,
and
then
it
will
know
where
to
put
it
okay.
A
So
if
we
can
get
that
done
and
then
write
it
down
to
make
it
very
clear,
then
anybody
that's
working
on
pl
can
just
say:
hey
here
you
go
here's
my
bin
file
and
it
will
work
with
the
with
whatever
is
on
with
the
kuiper,
build
that's
on
the
sd
card
without
anything
else.
So
that's
kind
of
the
current
challenge
on
that.
It
seems
like
it's
like
at
the
high
level.
A
All
of
analog,
I
mean
so
all
of
analog
devices.
Technical
support
and
customer
support
is
supposed
to
be
through
the
engineer
zone
forum,
which
swatto
has
used
to
try
to
talk
about
nfs
and
all
and
then
paul
chimed
in
on
that
thread
and
just
like
over
at
xilinx.
This
is
the
exact
same
situation
at
xilinx.
Xilinx
wants
you
to
use
their
forums
yes
and
wow.
What
a
jungle
that
is,
you
can
find
treasures
and
trash,
and
then
you
you're
reading
along
and
you're
like
oh,
this
is
exactly
it
and
you
realize
it's
from
2016.
D
A
So
as
soon
as
we
can
figure
this
out,
then
we
need
to
write
it
down
and
have
it
on
our,
at
least
on
our
repo,
and
you
know
feed
it
back
to.
Hopefully
it
will
be
findable
enough,
so
that's
kind
of
the
if
there
is
a
better
way
forward
other
than
like
a
device
tree
overlay
and
letting
linux
do
the
thing,
and
then
you
just
put
your
new
bin
file
in
the
firmware
directory.
That's
accessible
to
you!
A
That's
kind
of
the
nice
thing
is
that
it
doesn't
require
me
to
pull
the
sd
card,
go
and
rebuild
everything
and
then
put
it
back
in
because
that
would
just
slow
people
down.
You
know
the
having
people
be
able
to
drop
it
off
in
a
directory
that
they
have
access
to
that's
much
better.
You
know
to
get
me
out
of
the
loop
as
much
as
possible
should
be
the
goal.
So
that's
that's
the
stan.
That's
the
status
here
any
other
better
way
forward,
though
I
am
willing
to
dive
right
in
and
and
try.
B
A
D
Yeah
got
you
so
where
I
left.
I
was
working
on
a
project
that
thomas
has
created
using
one
again,
the
you
know
using
one
of
the
sample
designs
from
adi,
where
he
just
took
a
small
sample
of
hdl,
which
includes
j
j
est
and
he
simplified
it,
and
what
we
were
trying
to
do
is
get
the
ps
to
interact
with
pl
and
get
the
data
out
of
the
air.
D
D
D
D
C
Not
long
in
the
initial
phase,
just
an
hour
or
two
and
then
later
on,
when
I
actually
I'm
able
to
do
yeah.
Actually
that
may
be
it.
If
there's
a
second
phase,
it
would
take
more
like
half
a
day
if
it
takes
longer
than
that
I'll
back
out
and
put
it
back
where
it
was
because
it
shouldn't
be
that
complicated.
C
C
A
C
D
C
What
I
posted
describes
both
phases
and
the
first
phase-
is
just
to
get
the
the
big
and
the
tools
directories
mounted
on
the
system
and
then
the
second
phase
is
to
move
the
data
from
the
one
to
the
other,
and
I
can
do
some
moving
and
I'll
ask
individual
users
to
do
their
own,
because
that
way,
they'll
know
where
it
ended
up,
or
I
can
help
with
that.
I
can
move
stuff
for
people,
but
it's
better.
If
everybody
knows
what's
going
on
and
has
their
fingers
on
it.
D
A
A
A
Following
your
suggestions,
I
probably
will
need
some
some
help
and
looking
looking
forward
very
much
to
the
ps
and
the
pl
side,
working
together
with
onshore's
work,
so
I'll,
be
here,
we're
looking
forward
to
hamcation,
so
we'll
be
traveling
on
february
9th,
but
that's
still
days
and
days
in
the
future,
so
plenty
of
time
for
all
sorts
of
wonderful
progress.
Thank
you.
Everybody.
D
A
Yeah,
I
think
sawato
already
asked
for
that,
and
that
was
that
was
requested
last
week
as
well.
So
I
did,
I
did
take
a
I
have
started
on
making
it
putting
it
all
in
one
place
on
like
what
I
what
I
did
so
yes
and
I'm
gonna
write
it
down
again
so
it'll
happen,
and
this
is
like
just
re
just
being
able
to
recreate
the
custom.
Ip
part.
Is
that
the
the
main
I.
A
Got
it
yeah?
Fortunately,
there
is
actually
some
good
there's
a
pretty
good
document
from
from
adi
that
I
that
I
linked,
but
it
it
assumes
an
off
that
you
know
an
awful
lot,
so
so
those
sorts
of
things
that
I,
and
also,
if
you're.
So,
if
you're,
if
you
have,
if
you
have
created
raw
rtl
files,
completely
very
simple,
rtl
files,
that's
kind
of
what
they're,
assuming
if
you
have
a
fully
functional,
complex
sort
of
module
with
anything
extra
that
you're
doing
like
the
wrapper
trick
or
the
port
type
trick.
A
This
is
very
well
written
code
from
swato,
so
but
yes
I'll
I'll,
fill
in
and
show
that
that
he's
actually
provided,
he
has
a
tackle
file
that
actually
does
at
least
part
of
the
job
that
the
tackle
file
from
adi's
template
was
doing
so,
including
both
of
them
was
kind
of
part
of
the
problem.
So,
yes,
I
will
get
a
some
sort
of
here's
the
workflow,
because
that's
what
we
want.
A
We
want
people
to
show
up
and
to
be
able
to
put
their
their
custom
ip
into
the
reference
design
without
anybody
else
having
to
fuss
with
it
or
assist
like
as
long
as
you're
willing
to
like
read
the
document,
and
you
understand
the
basics
of
fpga
design.
You
should
be
able
to
participate
and
put
your
put
your
stuff
into
the
really
nice
reference
design
that
analog
devices
provides
so
yeah
a
guide
or
documentation
is
definitely
a
high
priority.
A
I
think
that
the
the
time
where
it
will
be
complete
is
probably
when
this
encoder
works,
and
I
can
then
say:
okay,
so
now
you're
working
with
a
board
that
uses
jesde
and
dma.
How
do
you
take
advantage
of
that?
And
that's
the
kind
of
the
last
puzzle
piece.
Well,
maybe
not
the
very
last
one,
because
you
need
to
have
a
source
and
we
think
we
can
provide
that
through
iio
api,
so
cross,
all
fingers
and
and
then
everything
will
flow
through
this.
A
This
really
nice
design
and
then
show
up
on
the
air,
and
then
people
will
be
able
to
see
that
so
so
the
answer
is
a.
I
guess
that
was
a
very
long
answer
to
your
short
and
and
excellent
question,
and
the
answer
is
absolutely:
yes:
it's
it's
it's
gonna
be
there.
Will
there
will
definitely
be
comprehensive
documentation
on
how
to
take
advantage
of
it.