►
From YouTube: AWG 230523 Meeting
Description
Presentation by Benjamin Prautsch of Fraunhofer on automating analog design.
A
Today
so
I'd
like
to
welcome
Benjamin
pouch
today
to
our
analog
work
group
meeting
I'm
hoping
helping
many
by
the
way
help
host
us
today,
as
many
is
traveling,
so
appreciate
that
but
I
look
forward
to
your
chat,
Benjamin
and
then
after
that
hung
ji,
we'll
be
providing
an
update
on
his
work.
After
that,
so
Benjamin
go
ahead.
B
B
A
B
All
right
so
now
now
I'm
on
track.
So
please
excuse
this.
First
of
all,
it's
I
would
like
also
to
stress
that
the
work
that
I
present
is
largely
supported
and
funded
by
the
German
Federal
Ministry
of
Education
and
Research.
So
we
do
a
lot
of
research
activities.
We
also
do
industry
activities,
but
that's
yeah.
B
Here,
that's
the
acknowledgments
to
the
funding
we
have
been
receiving
for
a
while
and
that
we
have,
and
that's
still
going
on
and
I
would
like
to
start
with
a
brief
introduction
of
round
hover
itself,
because
so
it's
maybe
not
exactly
clear
who
or
what
frown
over
is
so
Fraun
hover
gazelle
shaft
is
yeah.
It's
an
application,
oriented
research
facility.
It
tries
to
bridge
the
gap
between
University,
Research
and
Industry
and
yeah.
We
have
roughly
30k
yeah
employees
at
fraunhofer
all
across
Germany,
so
everywhere
in
Germany.
B
There
is
an
Institute
and
we
have
76
institutes
all
across
Germany
with
a
budget
two
years
back
2021
with
2.5
billion
and
the
funding
structure
is
such
that
one
third
roughly
is
or
say:
70
is
either
a
basic
funding
or
funding
or
research
projects
and
30
is
yeah.
What
we
also
work
together
with
yeah
companies
in
order
to
really
implement
this
bridge
in
the
gap
between
University
and
Industry
tree,
and
we
belong
to
the
fraunhofer
institutes
for
integrated
circuits
IIs.
B
That's
the
largest
of
all
different
institutes,
it's
located
in
barbaria
in
Germany,
a
thousand
parts,
and
we
here
specifically
are
located
in
Dresden.
So
the
heart
I
like
to
say
the
heart
of
silicon
Saxony,
that's
where
we
are
located
and
this
division
engineering
of
adaptive
systems
here
I
also
have
some
figures.
So,
for
example,
just
to
highlight
a
few.
We
have
quite
a
bit
of
laboratory
where
we
provide,
for
example,
a
measurement
for
also
for
customers,
and
recently
we
made
the
tape.
B
Oh
it's
down
to
five
nanometer
and
we
have
several
tape
outs.
We
work
on
the
design
side,
but
also
like
system
modeling
aspects
of
this
and
yeah
as
a
final
slide
of
this
AdWords
part
again
as
fraunhofer.
We
do
both
funding
projects,
but
also
can't
break
research.
So
this
means
on
one
hand,
side
we
might
appear
as
a
university,
but
in
fact
we
appear
rather
like
a
company,
so
this
means
individual
contract.
Research
can
always
be
aligned
with
us
based
on
individual
agreements.
B
This
might
might
be
education,
wise
might
be
consulting
or
workshops,
pilot
feasibility
studies,
yeah,
individual
project
ideas
or
the
licensing
of
Ip.
Might
it
be
hard
IP
or
soft
IP,
okay,
and
in
this,
in
this
Frame,
what
we
are
working
on
in
our
business
area.
Efficient
Electronics
is
as
one
aspect
of
the
design
of
microelectronic
circuits,
so
the
design
part
and
the
so
we,
of
course
the
manufacturing
is
done
by
a
third
party.
But
then
we
test
this
in
the
lab.
B
We
are
also
pretty
active
in
the
advanced
packaging
field
and,
of
course,
the
topic
of
today.
We
work
on
analog
design,
Automation
and
that's
exactly
what
the
focus
of
this
presentation
here
is
and
well
as
you
in
the
analog
working
group
of
course
know.
Well,
we
have
pretty
much
a
gap
between
analog
and
digital,
so
here,
to
put
this
in
some
figures.
While
on
the
digital
side,
we
do
have
synthesis
on
the
analog
side,
we
still
largely
have
manual
design.
B
Of
course,
there
are
especially
recently
a
lot
of
attempts
to
increase
automation
on
the
manual
analog
side,
but
the
major
challenge
still
is
that
what
maybe
it
takes?
A
few
tens
of
minutes
in
digital
might
require
as
much
as
weeks
or
even
month
in
analog,
and
that's
definitely
a
problem
too
well
SOC
designs,
and
if
we
dig
a
little
bit
deeper,
the
challenges
that
we
see
or
on
the
design
side.
B
Some
some
major
challenges
we
see
is
that's
due
to
the
low
level
of
analog
automation,
both
minioritization
and
Nano
scale
effects,
as
well
as
the
increasing
system.
Complexity.
Of
course,
yeah
get
more
and
more
a
challenge
to
to
to
the
design
problem
and
what
we
propose
a
solution
here
is
to
consider
both
two
aspects:
one
is
to
systemize
the
design
flow
and
and
second
is
to
automate
the
design
flow.
Our
approach
here
is,
and
I
will
detail
this
later
on.
B
It's
very
much
generator
based,
so
I'm,
automating
building
blocks
integrates
the
methods
into
the
flow,
and
here
we
follow
a
technology,
agnostic
approach
that
I
will
detail,
and
maybe
you
have
seen
the
presentation.
This
is
also
available
on
YouTube
from
Christoph
sandner
from
infinian,
so
because
he
made
a
slide
that
I
really
liked.
B
Therefore,
I
adapted
this,
so
that's
yeah
from
his
presentation
that
I
referred
down
there
in
the
typical
manual
design.
Of
course,
you
well,
you
have
to
design
faces
and
several
versions
of
Ip
and
it's
relatively
constant.
The
time
you
need
to
even
reuse,
IP
and
the
generator
based
approach
is
yeah.
B
This
reasoning
now
yeah,
we
tried
to
sketch
briefly
roughly
the
individual
design
steps
that
we
see
in
ic
design,
of
course,
starting
with
the
requirements
and
then
based
on
on
modeling.
It
runs
all
the
way
towards
sign
up
and
then
sign
off
and
then
finally
manufacturing
later
on,
of
course,
also
measurement.
But
here
the
focus
is
the
design
part,
and
today
this
is
pretty
much
done
manually.
Of
course,
the
in
the
well,
the
many
tools
improve
over
time
level
of
automation
increases,
but
essentially
it's
a
manual
task
design.
B
These
individual
tasks,
in
order
to
even
based
on
this
automation,
even
improve
the
level
of
reuse,
because
if
you
have
automated
an
individual
step,
you
can
preserve
this
for
later
on
and
then
re-run.
This
automation
step
and
that's
basically
automation
for
an
individual
design
step,
but
putting
the
pieces
together
in
a
consistent
flow
is
then
even
the
next
step
where
we
believe
yeah.
B
That's
the
way
to
go
in
the
mids
and
in
the
long
run,
but
today
the
focus
will
be
especially
on
the
circuits
design
side
and
on
the
layout
design
sites
a
little
bit
on
the
floor
planning,
but
also
on
the
layout
generator.
So
aspects
around
this
is
also
tasks.
That's
project
partners
are
working
on
or
where
yeah,
where
other
teams
at
our
in
our
institutes
are
working
on,
but
this
year
should
be
the
focus
for
today
and
I
would
also
like
to
bring
in
a
site.
B
It
is
just
a
secondary
source
but
I
like
the
site,
pretty
much
that
analog
circuit
design
is
like
chess
just
because
you
know
the
pieces
just
just
because
you
know
how
the
pieces
move
doesn't
mean.
You
know
how
to
play
the
game
and
I
think
there
are
some
yeah
interesting
yeah
thoughts
inside
one,
of
course,
is
to
even
know
the
pieces
and
then
also
to
know
how
to
put
the
individual
pieces
together
and
then
do
something
with
it.
B
And
I
would
like
to
yeah
trying
to
to
say
scratch
the
surface
about
some
of
the
pieces
and
maybe
some
ideas
how
they
could
play
together
and
one
yeah.
One
part
of
the
thought
process
that
we
had
was
that,
of
course,
on
the
manual
that
we
I
have
maybe
roughly
two
axes.
One
is
say
the
level
of
automation.
B
The
other
axis
is
the
hierarchy
level
like
how
complex
the
the
block
is.
That
is
automated.
That's
definitely
not
a
complete
map,
but
it
tries
to
to
sort
this
a
little
bit.
While
we
can
also
see
that,
of
course,
the
big
players
they
all
work
on,
design
acceleration
they
bring
in
in
new
tools
and
add-ons
to
improve
the
manual
design
method,
but
quite
a
bit
differently
works.
B
The
procedural
automation
where
really
parts
of
the
design
are
automated
very
much
known,
of
course,
are
the
P
cells
very
low
on
the
device
level,
but
based
on
those
results,
the
yeah
idea
was
adapted
best
known
from
my
point
of
view,
at
least
is
probably
the
Berkeley
analog
generator,
meanwhile,
even
in
the
third
version
available
and
even
open
source.
So
the
Mosaic
group,
for
example,
is
building
upon
the
findings
there.
B
This
is
now
by
the
way,
exactly
the
figure
that
midi
was
asking
as
far
as
I
understood
him.
So
the
underlying
methods
are
yeah,
three
Falls
or
could
be
categorized
like
this,
but
this
is
not
my
idea,
that's
from
Ricardo
Martins
at
all,
as
given
on
the
yeah
at
the
bottom.
So
we
have
procedural
approaches.
We
have
template
based
approaches
and
we
have
optimization
based
approaches.
I
will
detail
this
in
a
second
and,
of
course,
time
was
going
on.
B
That's
again
not
a
complete
list,
but
it
tries
to
highlight
a
few
of
the
approaches
as,
for
example,
the
Berkeley
analog
generator
on
the
procedural
side,
but
there
recently,
of
course
there
are
also
tools
like
a
line
and
metrical
in
between
the
Green
yeah
marked
Publications.
That's
our
those
are
our
contributions,
where
one
can
also
see
that
we
started
as
a
procedural
and
we
try
to
go
more
towards
template
based
and
optimization,
based
and
I
think
when
it
comes,
of
course,
to
open
source.
B
What
I
find
quite
interesting
is
that
especially
a
line
and
magical,
they
had
multiple
versions,
so
they
started
in
2019.
So
that's
the
latest
sources,
I
I
know,
but
then
yeah
came
up
with
updates
and
updates,
and
the
open
source
aspect
here,
of
course,
is
quite
driving
and
that's
something
we
are
also
looking
at
very
much
okay,
but
now
a
little
bit
deeper
dive
into
the
method.
So
I
mentioned,
there's
the
optimization
based
approach.
B
Some
nice
plots
with
trade-offs,
even
in
this
case,
even
considering
layout
effects
to
to
really
see
how
trade-offs
are
when,
when
even
layout
is
considered
and
a
special
form
of
a
constraint
is
yeah,
it's
a
so-called
template
which
basically
might
be
understood
as
a
floor
plan.
It's
like
a
slicing
tree
like
this
one
also
here
this
is
from
from
a
paper
from
Castor
Lopez
at
Isle
back.
We
are
back
in
28.
B
and
the
underlying
idea
is
that's
based
on
the
templates,
which
is
just
a
relative
placement.
The
actual
implementation
can
be
found
like,
as
you
can
see
here,
for
example,
Block,
M
and
F.
They
are
always
located
roughly
at
the
same
place
because
the
relation
is
stored,
but
the
actual
implementation
of
shape
and
and
size.
This
is
part
of
the
optimization
process
and
then,
of
course,
like
filling
the
gaps
by
proper
alignments
or
sizing
or
even
building
block.
B
Parameterization
is
crucial
here
and
the
actual
geometry
that
is
generated
underneath
the
templates,
that's
where
we
get
to
the
procedural
generators
and
that's
essentially,
we
are
a
programmed
procedure
that
takes
parameters
and
outputs,
for
example,
layouts
or
any
other
sort
of
data,
and
the
underlying
idea
here
is
that
well
not
in
an
iterative
way.
It
is
analyzed
what
the
solution
could
be,
but
it's
rather
a
known
strategy
that
is
coded
into
the
procedure.
There
might
be,
of
course,
some
conditional
statements.
B
There
can
be
a
lot
programmed
inside,
but
the
basic
idea
is
that
something
known
will
be
used
and
is
essentially
rerun,
and
this
is
already
used,
of
course,
in
analog
design
today,
because
we
are
probably
almost
all
the
basic
building
clocks
like
here.
Transistor
building
clocks
are
Auto
automated.
As
of
now
it's
it
didn't
well
that
that
was
not
the
case
in
former
times,
but
today
I
at
least
in
my
experience.
B
There
are
not
so
many
that's
yeah
customized,
even
those
building
blocks,
and
if
they
do,
they
would
likely
Build
A
P
cell
out
of
it.
If,
for
example,
they
would
like
to
have
a
very
special
transistor
shape,
but
then
we
already
see
the
Automation
and
now,
of
course
they
came.
The
question
like
how
to
benefit
further
from
such
generators
and
the
well.
B
What
we
focus
on
is
to
make
it
user
driven.
So
that's
designers
have
control
like
in
the
piso
and
that
they
can
Define
and
parameterize
various
aspects
of
the
generation
result,
while
the
generator
method
itself
is
spreadly,
pdk
agnostic,
so
we
have
been
using
iip
in
350
down
to
22.
Nanometer
now
made
some
first
proof
of
Concepts.
B
Internally,
so
to
see
how
the
the
method
runs-
and
we
always
use
the
P
cells
from
the
pdk
as
part
of
the
generated
structures
from
well
that
our
generators
are
built
and
the
another
differentiation
to
P
cells
is
that
the
full
design
data
is
really
generated
so
right
in
the
design.
Library
data
will
be
generated
in
a
persistent
fashion,
but,
of
course,
by
the
design
methods
or
by
the
iip
method.
It
is
parameterized
and
I
already
mentioned
this.
B
This
challenge
about
low
complexity,
but
High,
reuse
and
high
complexity
and
low
reuse,
and
this
led
us
to
we
are
to
basically
three
main
applications
for
for
the
generator
method.
So
we
already
built
an
iip
our
framework
that
we
call
the
IRP
framework
where
all
the
flow
integration
Etc
is
is
implemented,
also
the
handling
of
Technologies.
B
So
this
is
what
we
also
offer
to
to
customers
and
then,
on
top,
we
have
basically
three
modes
of
how
we
believe
generators
can
be
applied,
so
one
is
kind
of
the
out
of
the
box
generator,
that's
like
kind
of
a
default
generator
for
default
building
blocks.
Second
is
a
pillar
of
reuse
where
yeah,
when,
when
reporting
from
one
technology
to
another
or
from
one
specification
to
another,
the
generators
can
accelerate,
and
the
third
is
really
that
based
on
custom
needs,
a
custom
generator
is
built.
B
This
might
be
by
our
method.
This
might
be
by,
for
example,
skill
programming,
but
this
is
basically
yeah.
The
categories
that
we
identified
is
probably
worth
thinking
of.
Okay
and
I
would
not
now
like
to
go
a
little
bit
yeah
through
those
through
those
pillars.
To
give
you
an
idea
of
our
method
and
also
of
our
underlying,
we
are
thinking
of
the
approach.
B
So
here
is
basically
the
first
pillar
where,
on
the
right
hand,
side
you
can
see
a
schematic.
There
are
building
blocks
which
are
already
generated
so
as
you
yeah
as
Illustrated
here,
the
generator
user
interfaces
in
the
middle
and
using
this
you
can
build
up
the
schematic
in
this
Block
Level
fashion.
B
As
the
whole
design
data
is
generated
to
all
those
blocks.
There
is
already
a
layout
corresponding.
You
can,
of
course,
customize
the
layout,
for
example,
a
number
of
rows
of
unit
devices
and
many
other
aspects
like
routing
with,
for
example,
but
but
this
layout
view
is
already
in
place
and
the
generator
allows
to
yeah
Define
the
specifics.
B
So
this
is
mainly,
of
course,
the
device
sizing,
but
also
those
layout
parameters,
and
while
this
can
be
used
in
a
GUI
mode,
this
can
also
be
used
in
a
scripting
mode
and
with
this
approach,
flow
flow
can
be
automated.
For
example,
they
are
running
by
using
a
parameter
file
or
by
sending
just
the
command,
with
parameters
to
to
the
Cadence
cre,
for
example,
okay.
But
to
give
you
an
even
more
impression
how
the
generator
works.
I
have
a
screencast
here
for
you.
B
So
in
this
case
now
a
unit
device
sizing
is
adapted,
the
generator
is
run
in
the
background
and
then
the
generator
building
clock.
In
this
case
here,
the
topology
was
already
predefined.
One
can
basically
build
up
the
schematic
and
if
you
now
yeah
start
at
the
schematic
and
run
the
schematic
driven
layout,
then
we
can
basically
go
through
the
typical
routine
and
on
the
right
hand,
side.
You
see
how
the
generated
building
blocks
corresponds
to
the
schematic
level
building
blocks.
B
So-
and
this
is
exactly
what
I
just
mentioned
before-
automation
on
the
building
clock
level,
as
here,
for
example,
for
differential
pairs
because
there's
a
special
generator
for
differential
pairs.
But
there
are
some
more
generic
generator
for
very
arbitrary
structures,
and
this
is
basically
the
mode
on
yeah
schematic
level,
design,
entry
and
then
usage
on
the
layout
level
to
accelerate
the
design,
and
this
was,
for
example,
used
here
in
a
project
in
in
22.
That
was
the
Tsar
ADC.
B
So
here,
for
example,
roughly
60
speed
up
could
be
reached.
So
you
see
not
all
the
blocks
were
automated,
but
the
designer
decided
for
some
blocks
to
be
automated
and
yeah
and,
on
the
right
hand,
side
the
fields
that
are
marked
they're,
also
automated
in
parts.
So
that's
basically
a
combination
that
is
always
possible
that
designers
can
decide
what
parts
they
automate
and
what
they
still
do
manual
or
another
example.
B
Here
in
130,
nanometer
pdk,
on
the
left
hand
side,
you
see
the
plane
devices
so
just
the
P
cells
on
the
right
hand,
side.
There
is
a
scenario
where
the
devices
were
already
encapsulated
in
building
blocks
like
current
mirrors,
differential
Pairs
and
in
both
cases,
the
placing
route
or
the
placement,
the
auto
place
from
the
design
environment
was
used
and
yeah.
Here
you
could
well
in
in
this
case
yeah.
The
amount
of
complexity
could
be
reduced
into
the
building
blocks.
B
Okay
back
to
the
three
pillars,
of
course,
you
yeah,
you
are
not
always
happy
with
some
some
generic
Solutions.
So
what
we
also
identified
is
that,
depending
on
the
problem
of
course,
we
will
need
some
custom
generators
and
the
typical
flow
with
custom
generators
is
always
that
there
will
be
a
phase
where
the
generator
is
specified
and
that's
exactly
again
what
I
mean
with
this
read
spots,
design,
experts
and
Eda
experts
really
have
to
understand
each
other
to
find
those
parts
of
the
design
that
are
reasonable.
B
Well,
where
it's
reasonable
to
automate,
then
it
happens.
The
actual
generator
implementation
in
order
to
then
apply
it
for
design
some
we
applied.
This
specific
methods
is
given
here
quite
a
while
back.
We
implemented
a
flash
ADC,
for
example,
just
to
see
how
how
far
we
could
get
in
terms
of
of
the
complexity
and
also
to
how
much
we
can
reuse
from
from
a
former
design.
So
there
was
basically
a
design
already
done,
and
this
manual
design
was
then
implemented
as
a
generator.
B
So
there
was
like
roughly
half
a
four
or
four
months
or
so
of
implementation
to
have
the
generator
at
hand,
which
then
was
running
in
both
or
we
are
executing
in
both
180
and
350
nanometer
and
was
also
flexible
in
in
the
resolution.
In
this
case
another
example
that
was
for
an
interface
generation
where
we
wanted
to
make
sure
that
the
right
net
is
located
and
on
the
right
spots
in
the
layout.
B
Here
we
simply
identified
well,
we
need
some
scripting,
because
the
designers
they
were
doing
similar
shape,
drawing
over
and
over
again.
So
here
the
simple
answer
was
we:
we
are
built
a
small
user
interface
and
skill
scripting
in
order
to
automate
exactly
those
repetitive
tasks,
and
this
is
exactly
the
underlying
idea
of
a
procedural
generator,
but
just
applied
here
by
means
of
some
some
skill
commands
and
one
final
example
where
we
also
identified
that
this
is
or
can
be,
a
good
sweet
spot
is
the
automation
of
test
structures.
B
Here
we
extended
the
generator
also
by
a
small
GUI.
That's
yeah
reflected
some
some
routing
schemes,
and
this
was
again
also
file
driven,
so
the
file
was
loaded
by
the
generator.
The
mask
is
still,
there
could
be
changed,
but
doesn't
have
to
be
changed
because
the
input
file
in
this
case
was
basically
an
Excel
sheet
and
based
on
the
Excel
sheet
and
different.
B
B
B
Then
there
comes
one
procedure
that
prepares
data
in
order
to
make
sure
that
data
is
similar
across
on
the
target
views,
and
then
we
basically
have
the
individual
views
as
the
schematic
or
the
layouts
symbol
is
not
highlighted.
In
this
case,
and
in
order
to
even
reduce
yeah
to
reduce
the
efforts
here,
we
have
a
tool
that
we
call
the
IRP
Creator,
which
is
a
tool
that
takes
an
existing
schematic
and
makes
a
Fields.
B
Basically,
this
structure
with
all
the
information
like
all
the
P
cells,
all
the
wires,
all
the
pins,
all
the
sub
generators
into
this
generator
structure
in
order
to
help
generate
a
developers
to
build
their
own
generator,
and
this
now
basically
brings
us
to
this
yeah
middle
pillar.
That
I
also
mentioned
before
this
path
of
reusing,
reusing
designs
and
here
the
idea,
basically,
is
we
start
with
a
design,
have
a
tool
to
make
code
out
of
this
design.
B
So
the
the
layout
part
is
not
yet
covered.
But
that's
under
construction
and
then
use
this
generated
code
to
run
the
generator
either,
for
example,
across
flavors
or
across
pdks,
in
order
to
yeah
have
enable
reuse
and
the
more
we
use
generators
in
the
source
design,
the
more
we
can
benefit
on
in
the
Target
design,
and
here
in
order
to
also
illustrate
how
this
appears
to
the
user,
we
can
select
the
generated
generator.
B
Fully
automated,
so
there
was
no
programming
involved
to
reach
the
state.
We
see,
on
the
left,
hand,
side
various
parts
in
the
tree
and
here
with
a
list
of
sub
generators
that
are
all
generated
by
this
main
generator,
and
if
now
the
apply
button
is
hit.
In
this
case,
roughly
a
minute,
you
see
the
design
the
library
fills
up
with
with
building
blocks
and
those
building
blocks
cover
schematic
symbol
and
layouts
and
yeah.
B
As
you
can
see
here,
it's
always
all
those
three
views
and
therefore
they
are
reflected
on
the
yeah
on
on
the
design
side.
So
we
have
basically
the
source
schematic.
Typically,
it
doesn't
change
pretty
much,
but
of
course,
a
lot
of
the
details
will
change
in
the
on
the
layout
side
and
that's
basically
the
the
approach
of
the
IRP
Creator.
But,
as
you
can
see,
the
layout
is
basically
just
placed
side
by
side
and
that's
yeah,
more
recent
activity
that
we
did.
This
is
where
we
really
embedded
this.
B
Those
templates
that
I
mentioned
in
the
beginning
that
we
Implement
that
them
into
the
generator
here
a
simple
example:
on
the
left
hand
side
you
have
the
user
interface
in
the
middle.
You
have
a
representation
of
the
template,
but
there
are
no
Dimensions.
So
a
template
does
only
know
a
relative
locations
and,
on
the
right
hand,
side.
B
This
then
back
into
the
flow-
and
this
now
brings
me
back
to
this
figure
that
I
showed
in
the
beginning.
So
we
I
showed
these
individual
steps.
I
showed
what
runs
manual
today,
I
showed
what
we
proposed
to
set
up
to
automate
and
yeah.
This
way
designers
can
build
circuitry,
they
can
automate
their
own
generator
built
on
generates
yeah
generate
initial
layouts
then
of
course
make,
for
example,
the
the
post
layout
simulations
and
relatively
quickly
run
this
yeah.
This
iterative,
Loop
okay.
C
B
So,
while
there
are
tasks
where
generators
really
can
help,
there
are
tasks
where
design
experts
should
yeah
take
and
have
the
control
and
I
think
it's
always
important
to
to
align
really
what
should
be
automated
and
what
should
be
done
by
the
by
the
designer
and
for
for
this
reason
we
are
always
propose.
Whenever
such
a
problem
appears
Eda
experts
design
experts
should
make
a
workshop.
B
This
is
also
what
we
offer,
but
in
in
general
they
they
should
really
sit
together
and
then
maybe
iterate
make
some
first
tests,
try
out
ideas
and,
and
only
then
gets
into
in
the
actual
integration
phase
well
and
yeah.
Finally,
some
some
conclusion
here:
analog
IC
design,
as
you
of
course
know,
is
complex
and
challenging
the
yeah.
The
communication
between
design
experts
and
Eda
experts,
yeah
I,
believe,
is
really
the
key
to
enable
and
improve
analog,
Automation
and
there's
probably
not
a
one-size-fits-all
solution.
B
So
there
should
always
be
an
alignment
of
combining
methods.
That's
that's.
We
are
also
made
reasonable,
reasonable
parts
of
the
design,
and
this
is,
of
course,
all
based
on
really
good
alignments
among
the
domains,
Eda
and
design
and
yeah,
based
on
a
good
understanding
that
either
of
them
really
understand.
What's
what
the
other
is
talking
about
is
probably
the
key
to
yield
this
sweet
spot
and
that's
basically
the
yeah,
the
underlying
idea
that
I
wanted
to
yeah
to
bring
because
the
question
was
well,
there
are
chances,
there
are
hurdles.
B
Communication
is
probably
one
of
those
hurdles,
but
there's
also
a
good
chance
to
really
accelerate
analog,
to
get
rid
of,
maybe
not
so
nice
tasks
and
even
improve
the
design
performance
in
this
mixture
of
Eda
and
design,
and
with
this
thanks
for
your
attention
here.
This
is
also
my
contacts
or
your
information.
C
A
A
But
you
know
one
of
the
things
that
I've
been
advocating
for
along,
amongst
others
in
industry,
for
quite
some
time,
is
really
what
I
would
call
as
an
Eda
toolkit
approach,
which
is
effectively
that
the
major
Eda
suppliers,
which
have
a
of
course,
a
very
stable
design
platform,
make
their
tools
more
like
a
toolkit
and
something
Beyond,
just
a
tickle
or
python
API
right.
So,
like
the
work
you're
talking
about,
you
really
need
low
level,
Source
level
access
to
be
able
to
do
the
things
that
are
required
by
the
design.
A
B
B
So
if
you
just
consider
individual
steps
along
the
design
flow
in,
say,
more
or
less
close
design
environments
where
you
can't
really
like
well
get
full
access,
as
you
just
put
like,
if
there
is
maybe
some
skill
or
some
tickle
scripting,
and
if
you
want
to
link
python
into
it,
then
you
need
to
build
your
bridge,
and
this
is
always
yeah,
not
really
not
really
included.
I.
Think
well,
I!
B
Think,
that's
that's
something
that
we
can't
really
solve
technical
technically,
but
this
is
rather
a
business
model
decision
of
the
big
players.
So
I
I,
don't
know
the
exact
details,
but
recently
it
was
announced
that
maybe
Cadence
will
open
the
environment
a
little
bit
more
to
at
least
like
plug
in
other
optimizers
for
the
simulation.
But
I
don't
exactly
know
the
details
but
I
think
well.
Maybe
the
open
source
trend
is
pushing
this
a
little
bit,
but
but
I
also
see
the
yeah
different
interests
and
I.
B
C
B
It's
the
topic
of
openness
right:
it's
it's,
both
research
and
and
the
services
we
provide,
so
everybody
who
is
interested
in
having
such
a
generator
evaluating
it
or
using
its
in
design
either,
either
as
like,
ready
generator
or
as
the
tool
itself
that
you
could
Implement
and
Implement
generators.
That's
exactly
where
we,
where
we
are
located
here
on
both
sides
of
the
spectrum.
So
we
do
have
funding
projects
where
we
developed
large
parts
of
the
software
and
in
specific
contract
research.
D
Do
you
have
a
portfolio
right,
so
automation
I
mean
it
sounds
like
you're
able
to
do
some
information
there,
but
then
what
are
the
building
blocks
for
portfolio
of
ips
you're
able
to
generate
here
and
how
do
you
you
know?
How
do
you
compare
because
you
mentioned
at
some
point-
magical
and
Alliance?
So
how
do
you
compare
to
these
tools?
Have
you
been
able
to
run
them.
B
B
The
Berkeley
analog
generator
is
also
very
much
on
this
programming
side
of
the
spectrum,
so
I
think
the
com.
Well,
the
key
comparison
is
that
we
combine
the
automation
with
yeah
with
the
service.
On
top
so
yeah,
we
we
can
use
our
methods
for
you
specific
yeah,
design,
problem
design,
challenge
regarding
yeah
available
IP,
as
our
colleagues
that
are
into
design
also
use
our
method.
We
have
several.
B
B
Yes,
well,
the
essentially.
This
method
here
is
mainly
really
the
the
Eda
side
of
the
spectrum,
so
I
did
did
just
show
a
few
examples.
Like
ADC,
we
also
had
other
adcs
really
programmed
in
the
past,
but
that's
what
we
identified
over
time.
That's
it's
better
to
yeah,
really
build
the
design
or
that
might
even
include
the
whole
generator
as
Eda
as
as
in
yeah
as
an
offer
that
we
build
together
with
the
customers
specifically.
B
So
we
we
do
not
really
have
this
catalog
of
generators
that
we
could
offer,
because
in
the
past
it's
basically
it's
I,
guess
it's
pretty
similar
to
to
the
IP
business.
There
are
also
many
IPS
available,
but
then
then
there
are
some
some
updates
and
changes
needed,
and
what
we
face
is
that
this
also
reflects
the
topology,
and
this
means
it's
probably
best
to
build
on
such
a
generator
together
with
a
customer
right
away
or
provides
the
methods.
B
So
this
is
a
generation,
well
I,
guess:
well
the
the
template
approach.
The
idea
of
the
template
approach
that
we
just
included
recently
is
to
well
widen
the
the
spectrum
of
performances.
But,
of
course,
in
the
end,
if
you
have
one
topology,
you
are
pretty
much
in
one
spot
of
the
possible
design
space,
so
you
might
use
hierarchical
attempts
to
to
like
combine
different
types
of
Ip
or
even
parts
of
Ip
to
to
reach
a
broader
Spectrum
but
I.
A
E
You,
okay,
okay,
great,
so
so
because
Christianity
is
going
to
present
the
a
hyper
presentation
building.
So
please
allow
me
to
give
you
some
updates
from
our
side.
So
I
don't
have
the
presentation
today,
but
I'll,
just
if
it
possible
I'll
just
go
here,
go
for
it
like
this
and
we
have
done
the
room.
Temperature
measurement
of
Skyworld
100,
certain
technology
using
the
pope
card.
But
the
thing
is
that
we
have
to
prove
it
manually
automatic
workstation.
So
so
we
have
to
move.
D
E
E
A
D
Yeah,
so
just
to
get
some
background
here,
Rob
we
are,
we
discussed
that
yesterday,
with
trying
to
figure
out
is:
is
there
a
way
to
to
do
another
thing
or
any
other
nodes
and
there's
interest
in
trying
to
you
know
automate
some
of
the
structures
and
test
them
for
higher
temperatures?
So
we
already
did
that
with
nesting
mpw
five
and
six
and
seven.
A
D
E
D
Makes
sense
yeah,
so
the
other
thing
Rob
is
we're
trying
to
build
up
a
suit
of
small
test
cases,
and
this
test
structure
seems
very
relevant
to
an
organization
because
we
we
can
test
all
all
the
available
Eda
tools
right
like
align,
for
instance,
or
maybe
bag.
If
it's
open
and
what
Benjamin
is
discussing
so
and
the
opening
face
off
obviously
and
see
you
know
we
can
develop
these
approaches
and
have
some
type
of
standard
here
in
ships
alliance
with
all
these
tools.