►
Description
Seminal work on the first ever 64 bit open source, Linux capable Instruction Set Architecture (ISA) for microprocessors. Note that the hardware is not open source, but the ISA is.
See FOSDEM 2018 - https://fosdem.org/2018/schedule/event/riscv/
-----
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A
B
Don't
turn
my
mic
on
okay,
thank
you.
I'm
Palmer
I'm,
the
maintainer
of
the
ports
of
various
open
source
project
service,
five,
including
binutils,
GCC,
Linux
and
GMC.
So
what
is
risk
five?
It's
a
risk!
5
is
a
free
and
open
is
a
standard
designed
for
every
computing
device.
That
means
from
the
smallest
embedded
IOT
device
to
the
largest
supercomputer.
Oh
good,
good,
it's
working
right,
so
the
the
the
the
risk
5
has
been
around
for
a
while.
B
But
the
major
watershed
moment
in
the
last
week
is
that
the
risk
5
port
GFC
has
been
submitted
upstream
and
released
quickly
after
that,
which
means
that
now
the
core
components
of
the
Linux
software
stack
have
been
ported
to
risk
5
and
are
available
in
tarball
releases
from
upstream.
That
means
that
it's
now
time
to
start
porting
your
favorite
software
project
to
risk
5.
So
what
I'm
here
to
do
today
is
to
convince
you
to
join
our
revolution
so
good
it
went.
B
So
why
are
is
a
is
important,
so
the
I
say
is
the
most
important
interface
in
the
computer.
So
it's
the
reason
that
Intel
can't
break
into
the
mobile
market.
It's
because
the
mobile
software
has
largely
ported
for
armed
systems
simulator.
It's
the
reason
that
arm
can't
move
into
the
server
market,
because
server
software
largely
expects
Intel
systems,
and
this
is
despite
large
investments
in
software
infrastructure.
B
Over
the
years,
I
went
to
a
talk
earlier
today
about
porting
code
from
Python
2
to
Python
3
in
it
it
was
a
10-year
process
right
now,
IBM's
360,
the
longest-lived
is
a
Hizb
around
for
50
years
and
will
probably
outlive
all
of
us.
So
it's
a
it's
a
very,
very
important,
it's
a
very,
very
important
interface,
and
there
is
no
free
and
open.
Is
it
now
free
and
open
standards,
as
we
know,
have
worked
well
all
across
the
software
sack?
B
A
great
example
is
in
networking,
Ethernet
and
tcpip
have
taken
over
the
world
because,
basically,
nothing
left
additionally
operating
systems.
Largely
you
know,
somewhat
POSIX
compliant
systems
are
everywhere
and
in
graphics.
Opengl
is
a
great
example.
You
can
run
your
3d
applications
on
systems
from
multiple
vendors
and
they're
largely
portable.
So
why
is
there?
No
free
and
open
is
a
standard.
Well,
it
turns
out
that
it's
dominated
the
field
is
dominated
by
proprietary,
ices
and
they're,
really
not
great
designs,
so
risk
5
is
a
high
quality
license.
B
Free
royalty-free
is
a
specification
and
it
was
originally
designed
at
UC
Berkeley.
The
standard
is
now
maintained
by
a
nonprofit
organization
like
many
other
industry
standards,
it's
suitable
for
all
types
of
computing
systems,
from
smallest
I
Oh,
tea,
microcontrollers
to
the
largest
supercomputers.
Numerous
proprietary
and
open
source
cores
exist
it.
It
is
currently
experiencing
a
rapid
growth
in
industry
and
academia
and
also,
as
I
recently
mentioned
much
software
has
been
ported
to
it
over
the
few
years
and
like
everything,
it's
still
a
work
in
progress.
B
So
for
those
of
you
less
familiar
with
the
RISC
5
is
a
we've
written
a
book
and
we're
giving
awake
signed
copies.
The
book
was
written
by
Andrew
Waterman
and
he's
signed.
The
pay
signed.
The
title
page
I
was
also
written
by
Dave
Patterson,
a
professor
at
UC
Berkeley.
The
book
is
titled
an
open
architecture
atlas
and
it's
designed
as
an
introduction
to
the
respond
is
a
design
for
students,
hobbyists
and
basically
anyone
interested
in
computers.
So
hopefully
you're
here
for
your
interesting
computers.
B
So
if
you
want
to
get
your
copy
of
the
book
tweet
a
photo
of
the
talk,
it's
hashtag
hi-5
unveiled
and
at
sy5
inc
and
we're
going
to
select
the
winners
during
the
talk
we
have
ten
books
there's
more
than
ten
people
here,
which
is
good,
so
yeah
tweeted
us
during
the
talk
and
we'll
give
them
away.
So
now,
I'm
gonna
talk
about
the
origin
of
risk
five,
so
we've
been
developing.
This
is
a
for
thinking
about
eight
years
now,
and
you
might
say
so.
Why
did
we
start
designing?
B
Our
own
is
a
well,
so
we
were
at
Berkeley
and
we
were
trying
to
do
computer
architecture,
research
and
if
you're
gonna
build
a
processor,
you
need
an
highest
set.
So
we
wanted
to
look
around
at
the
existing.
The
existing
is
a
is
and
the
only
reasonable
choices
at
the
time
were
x86
and
arm.
Those
are
kind
of
the
two
market
leaders
we've
done
projects
based
on
other
systems
and
they
were
largely
obsolete.
So
x86
is
kind
of
the
obvious
choice
because,
particularly
at
the
time
it
had
the
vast
majority
of
software
support.
B
So
you
want
to
go.
Let's
just
look
at
kind
of
the
first
instruction
in
the
x86
manual,
which
is
the
AAA
instruction
right.
So
this
instruction
is
great
if
you're
trying
to
build
a
calculator
which
was
actually
what
the
x86
was
kind
of
regionally
designed
for
the
4004
was
sold
in
the
calculator
market.
So
basically,
what
this
does
is
binary
coded
decimal
support
makes
it
really
nice
and
fast
right,
and
it
turns
out
that
this
is
a
single
byte
instruction
on
modern
x86
systems
and
I
actually
went
last
night.
B
It
took
me
a
while
to
figure
out
how
to
get
it
into
the
assembler,
but
I
actually
managed
to
compile
an
AAA
based
program,
and
it
worked
actually
it's
kind
of
odd
when
digging
around
trying
to
figure
out
how
to
assemble
it.
I
found
out
that
the
286
had
a
little
bit
of
a
bug
in
its
AAA
implementation,
and
we've
maintained
compatibility
with
that
bug
until
today.
So
it
turns
out
that
not
only
do
we
have
a
legacy
instruction
designed
to
maintain
compatibility
with
calculators,
it's
not
even
really
quite
compatible.
B
So
if
Intel
can't
even
get
x86
right,
then
how
are
we
gonna?
Do
it
right?
So
the
next
option
is
arm
which
sounds
great.
It
stands
for
the
acorn
RISC
machine.
That
means
it's
probably
pretty
simple.
Alright,
so
let's
look
at
the
sorry,
LD
m.I.a
EQ
instruction,
which
has
so
many
letters
in
it.
It
can't
possibly
be
a
RISC
machine
alright.
So
what
does
this
do
right?
It
loads.
B
Multiple,
multiple
memory
addresses
from
the
stack
there
are
multiple
memory
addresses
it
increments,
another
address
which
means
that
it
writes
to
seven
registers
reading
six
from
memory
all
right,
it's
conditional,
so
it
only
executes
if
the
Equality
condition
code
is
set
right,
it
can
write
to
the
PC
because
on
arm
the
PC
is
an
addressable
register
for
many
instruction.
So
that
means
that
it
can
change
control
flow.
So
it's
effectively
conditional
branch
along
with
doing
a
bunch
of
loads
I.
B
Additionally,
it
can
changed
the
instruction
set
because
arm
encodes
the
thumb
instruction
set
in
the
lowest
bit
of
of
the
PC.
So
that
means
that
something
we
use
as
an
idiom
for
pop
the
stack
and
return
is
also
capable
doing
a
bunch
of
other
stuff,
which
is
a
recipe
for
disaster.
So
now
we
look
x86
and
are
really
aren't
viable.
B
So
at
the
time
we
started
a
three-month
long
summer,
Research
Projects
design,
our
own
ISA
and
four
years
later,
we
managed
to
actually
release
the
base
is
a
specify,
a
specification
weight
that
was
frozen
and,
of
course
it
took
us
four
years
because
we
were
doing
a
lot
of
things
in
the
meantime.
So
one
of
those
things
we
were
doing
is
we
were
taping
out
chips.
B
Hope
I've
got
myself
computes.
Yes,
sorry!
So,
while
we
were
taking
out
chips,
we
spent
a
lot
of
time
working
on
the
ISA,
and
we
are
quite
confident
that
it's
the
best
ISA
and
one
of
the
reason
is
because
we
have
lots
of
metrics
port.
So
remember
the
ISA
is
designed
to
scale
from
microprocessors
to
supercomputers,
so
one
of
the
most
important
metrics
for
a
microprocessor
I
say
is
the
static
code
size
because
you're
frequently
trying
to
cram
your
code
into
a
small
memory.
B
So
you
see
risk
v,
has
the
smallest
static
code
size
across
all
instruction
sets
arms
thumb
two
is
somewhat
close,
but
none
of
the
64
bit
destruction
sets
are
closed.
So
the
an
important
metric
for
supercomputer
or
high-end
implementations
is
the
number
of
dynamic
bites
fetched.
So
the
number
data
quite
stretches
or
largely
the
maximum
performance
you
can
get
from
the
machine
so
risk
v.
Has
the
smallest
number
of
dynamic,
bytes
fetched
across
all
instruction
sets
it's
smaller
than
x86.
B
B
In
order
to
tape
chips,
you
need
came
out
chips,
you
need
all
sorts
of
state-of-the-art
machinery,
for
example,
in
order
to
do
a
board,
you
need
a
state-of-the-art
reflow
facility,
which
we
built
with
a
toaster
oven
in
rhiness
this
kitchen
right,
because
there
was
no
other
way
to
do
it.
So
we
had
a
Raspberry
Pi
attached
to
a
temperature
sensor
and
we
would
match
the
reflow
profile
from
the
manufacturer
for
the
sauger
and
in
order
to
match
it.
B
You'd
turn
the
oven
up
a
little
bit
to
make
it
hotter
alright
and
then,
when
he
got
too
hot
you'd
open
the
door
a
little
bit.
So
we
cool
down
very
advanced
and
we
used
that
to
solder
the
board
for
the
for
us
22,
which
was
the
first
implementation
of
the
final
frozen
risk.
5
user
specification,
so
this
is
all
the
hardware
effort,
I'm
largely
a
software
person.
So
this
is
how
I
started
got
started
with
the
software
for
a
deeper
clean.
So
this
is
our
lab.
B
It
looks
very
different
than
the
hardware
lab
because
it's
a
software
lab
right.
It's
a
lot
of
desks,
but
it's
an
open
lab.
So
that
means
you
can
hear
what
everyone
else
is
doing
so
I
the
time
was
working
on
a
different
project
that
was
less
interesting.
There
was
five
and
I
heard
Andrew
who
had
been
designing
the
ISA
and
working
on
the
tool
chain
talking
to
Chris
who,
at
the
time
was
building
a
processor,
thinks
that
kind
of
right.
B
Next
to
each
other
right
and
I,
kept
hearing,
Chris
say:
oh
gee,
you
know,
gee
Lipsy
doesn't
compile
today
or
I
can't
figure
out
why
dry
someone's
getting
bad
components,
and
that
seemed
more
interesting
that
what
I
was
doing
so
I
thought:
hey,
I'll,
just
kind
of
go
help
out;
okay,
so
that
was
in
2012.
Two
years
later,
I
submitted
the
first
patch
to
an
open
source
repository
mentioning
risk
five.
So
this
was
a
like
a
two
line:
config
dot,
sub
patch
I
thought
this
was
a
really
big
deal
at
the
time.
B
Andrew
and
I
talked
about
it
for
like
an
hour.
We
pour
it
over
the
thing
to
try
to
get
it
right,
and
now
you
know
four
years
later
and
about
maybe
a
hundred
thousand
lines
of
code
more.
We
have
been
accepted
into
GFC,
Linux,
VIN,
utils
and
GCC.
So
the
whole,
the
core
of
open
source
I,
the
core
of
open
source
software,
is
available,
released
for
risk
by.
B
Gap
big
deal.
Thank
you.
Okay.
So
now
we're
gonna
switch
gears
a
little
bit.
I'm
gonna
talk
about
the
current
state
of
risk
pot,
so
the
current
state
of
risk
is
really
defined
by
the
risk
five
foundation,
so
the
risk
five
foundation
is
a
non-profit
foundation.
It
has
over
a
hundred
members
and
it's
it's
Charter
is
to
steward
the
risk.
Five
is
a
so
this
means
maintaining
the
iSight
specifications,
evolving
new
new
extensions
and
this
sort
of
thing
so
you'll
see
there's
a
lot
of
member
companies
up
here.
B
B
So
the
risk
5
specifications
are
really
the
core
of
what
the
risk
5
organization
maintains
and
the
risk
5
user
specification
is
designed
to
be
a
modular
specification.
So
this
means
that
you
don't
have
to
implement
either
the
whole
ISA
or
some
of
the
ISA.
Sorry
you
don't
have
to
implement
the
whole
is
a
you
can
implement
parts
of
the
ISA,
and
this
is
what
allows
us
to
be
scalable
to
implementations
both
from
the
low
end
all
the
way
up
to
the
high
end.
B
Alright,
so,
in
addition
to
the
privileged
ition
to
the
user,
is
a
specification
which
is
largely
what
you
interact
with
when
say:
writing
compilers
or
writing
user
code.
There's
a
privileged
mode
specification
and
this
privileged
mode
specification
allows
supervisor
software
to
run
so.
Linux
is
ported
to
the
supervisor.
Linux
is
ported
to
the
supervisor
mode.
In
the
provigil
size
specification,
we
also
have
a
hypervisor
mode
that
allow
hypervisors
to
run
okay.
B
So,
in
addition
to
these,
we
have
what's
called
an
external
debug
specification,
so
this
allows
you
to
bring
up
early
boot
software
by
a
JTAG
debugger,
and
this
is
a
very
important
component
of
I-
got
a
real
computer
systems.
It's
how
you
make
things
actually
work.
So
there's
one
specific
specification,
I'd
like
to
kind
of
call
out
on
its
own,
and
that
is
the
risk
five
memory
model,
so
risk
5
has
a
weak
memory
model
and
I
think
we're
unique
in
having
at
least
a
draft
of
the
formal
model.
B
That's
actually
been
kind
of
proven
to
match
the
you
know
the
pros
model
released
before
our
Linux
port
was
released,
and
this
was
really
nice
and
helped
us
actually
find
a
handful
of
bugs
in
the
linux
port,
as
we
were
up
streaming
it,
because
there
are
a
lot
of
very
smart
people
in
the
open-source
community
and
they
they're
willing
to
pour
through
memory
model
specifications
which
I
find
very
confusing
and
help
me
debug
my
code.
So
this
was
a
really
important
step,
and
this
is
something
you
could
only
really
get
with
an
open
standard.
B
The
real
key
development
in
the
current
state
of
verse,
5,
soft
scarra
stata
verse
5,
is
that
our
software
is
now
upstream,
as
I
mentioned
people,
so
binya
tells
the
pan
upstream
for
about
a
year
it
released.
Originally
in
2.28,
the
2.30
release
is
pretty
solid.
We
don't
know
of
any
major
problems
in
it.
It's
not
really
GCC
released
in
7.1,
maybe
six
to
nine
months
ago,
the
current
release
7.3,
which
also
came
out
a
few
days
ago.
B
It's
also
pretty
solid
that
can
compile
linux
and
much
of
user
software
necessary
stuff
linux,
which
released
about
a
week
ago
in
4.15,
is
the
first
release
with
risk
fives.
That
means
it's
kind
of
right
on
the
bleeding
edge,
and
things
tend
to
be
a
little
sticky
there,
so
particularly
for
linux.
That
means
that
none
of
our
device
drivers
are
upstream.
So,
while
nominally
there's
a
port,
it
means
you
can't
say,
take
an
interrupt
or
get
to
user
space
or
write
to
the
terminal.
B
So
it's
not
that
useful,
but
we
do
maintain
an
out
of
tree
patches
for
all
of
these
and
I
am
submitting
patch
sets
to
the
next
Linux
release,
because
the
merge
window
is
open
now
and
I
was
supposed
to
submit
one
on
Wednesday.
But
we've
been
writing
the
talk,
because
we're
very
excited
about
this,
but
hopefully
we'll
have
that
all
released,
probably
not
for
4.6,
but
hopefully
for
4.17
and
then
you'll
have
upstream
the
core
system
right.
Gmc
similarly,
was
very
recently
released.
B
2.17
came
out
on
February
first
a
couple
days
ago:
the
RV
64,
which
is
the
64-bit
support.
That's
largely
there,
but
RV
32
of
I
support,
which
is
our
32-bit
I,
say:
that's
not
in
their
port
exists.
We
have
it
out
of
tree.
We
just
didn't
have
time
to
get
it
kind
of
properly
bug
fixed
and
wanted
to
make
sure
that
what
we
submitted
was
stable
and
ready
to
use
and
the
most
important
target
for
reporting
say
Linux
distributions
and
such
is
the
64-bit.
B
So
no
I
am
a
maintainer
of
all
of
those.
But
I
couldn't
do
this
by
myself,
because
porting
software
is
a
massive
effort.
All
right
so
I'd
like
to
thank
the
various
other
companies
who
have
you
know,
allowed
their
engineers
to
help
me
port
risk.
Five
software
I'd
like
to
make
Berkeley,
who
still
pay,
is
a
couple
of
grad
students
to
maintain
risk.
Five
software
they're
still
left
over.
We
have
Red
Hat
who's.
B
Helping
maintain
gilepsy
blue
speck
is
helping
maintain
both
julep
C
and
G
B,
and
then
Andy's
has
done
a
lot
of
work
on
GCC
and
also
LLVM,
which
I'm
not
a
maintainer
of
but
I'm
very
happy
for
that
help.
So
that's
the
current
state
of
verse.
Five
we've
come
a
long
way
and
a
lot
for
in
the
last
four
years
now
I'd
like
to
talk
about
the
future
of
this
product,
so
that
there
are
some
deficiencies
in
our
Linux
port
in
G
live
support.
B
Some
large
deficiencies
there
also
a
few
small
ones
in
our
video
tools
in
GCC
ports.
So
one
of
these
is
that
our
linker
relaxations
or
quadratic
time
so
risk
5
uses
something
called
linker
relaxation
in
order
to
keep
the
is
a
small.
So
what
this
means
is
that,
instead
of
adding
a
bunch
of
a
distance
additional
addressing
those
to
the
ISA,
you
rely
on
software
to
implement
these
addressing
modes.
So,
for
example,
on
the
left
here
well,
I
have
a
point
you
can
see.
B
B
It
turns
out.
This
is
important
for
the
performance
on
a
lot
of
programs,
most
importantly,
dry
stone
which
still
drives
a
lot
of
people's
processor
buying
decisions.
Unfortunately,
but
it
means
that
we
get
very
good
dry
stone
performance
now.
The
problem
here
is
that
so
you
can
see
we
convert
the
lui
LW
pair,
which
is
an
absolute
addressing
mode
to
a
single
LW.
That's
GP
relative,
but
then
you
end
up
with
this
noah.
B
So
when
you
remove
the
no
hop
because
you
have
to
remove
it,
because
if
you
didn't
remove
it,
you'd
just
be
asking,
you
know
off,
but
still
take
the
same
number
instructions
who
wouldn't
help
you
all.
So
we
move
it
by
shifting
up
all
of
the
code
below
it
and
that
results
in
a
quadratic
time
link
for
us
v,
which
can
be
quite
slow
if
you're
linking
a
large
object,
particularly
if
you
run
into
something
like
linux
right.
So
we
have
some
infrastructure
and
bin
utils
for
doing
linear
time.
B
Linker
relaxation,
but
we
haven't
converted
all
of
the
relaxations
over
to
do
that.
So,
if
you're
interested
in
helping
out
in
risk
v
software-
and
you
like
hacking
on
bin
utils,
this
would
be
a
great
place
to
start.
So.
Similarly,
we
have
a
few
deficiencies
in
the
GCC
port
I
mentioned
Louie
and
LW
before
so.
In
this
case,
we
have
a
similar
program
that
loads
a
single
global
variable,
but
in
this
case
it
loads
it
twice
so
in
risk
bag.
B
We
have
two
addressing
modes,
we
have
absolute
which
uses
lui
and
we
have
pc-relative
which
uses
ali
pc.
In
both
cases,
you
have
two
instructions,
one
that
loads,
the
top
12,
the
top
20
bits
of
an
address
and
one
that
loads.
The
bottom
12
bits
it's
just
that
in
the
pc-relative
case,
you're
loading,
a
20-bit
PC
relative
offset
and
instead
of
a
20-bit
absolute
offset.
B
Okay,
so
I've
talked
a
little
about
respond
software
for
the
long.
For
the
last
few
years,
we've
been
maintaining
Forks
of
all
these
projects
in
our
own
github
organization,
which
is
github.com
slash
this
five,
so
there's
also
a
responding
list.
You
can
go
to
contribute,
but
now
that
we're
upstream,
the
development
is
moving
largely
to
the
official
repositories.
So
this
means
you
can
go
to
say
the
bean
details,
mailing
list
or
the
Linux
mailing
lists
and
contribute
to
the
respite
port,
just
like
you
would
with
any
other
project.
B
So
in
this
case
we're
really
excited
to
have
people
start
contributing.
So
if
you're
interested,
please
kind
of
pick
your
favorite
project
and
start
working
on
it,
so
I
mentioned
that
the
so
we're
talking
about
the
future
of
RISC
5.
So
in
this
case,
what's
really
gonna
be
coming
up
over
the
next
few
years.
Our
Linux
distributions
on
respond,
so
I've
talked
to
a
few
people
here
and
kind
of
IRC
whatnot
and
we
have
a
debian
port.
B
That's
going
it's
sort
of
in
the
process
of
being
bootstraps
early
in
the
process,
but
there's
work
being
done.
Additionally,
there's
a
fedora
port,
so
the
Fedora
port
is
also
in
the
process
of
being
bootstrap.
The
bootstrap
was
done
at
one
point.
It
was
for
a
slightly
older
version
of
the
ABI,
so
it
needs
to
be
redone,
but
hopefully,
over
the
course
of
the
year
we
can
have
fedora
and
Debian
come
up.
We
have
a
little
bit
of
support
for
us
five
and
openembedded.
B
We
have
some
of
the
core
tool
chain
support,
but
we
have
not
bumped
this
since
gee
Lipsy
came
up
and
hopefully
that
will
follow
on
soon
open
wrt.
We
have
a
maintainer
for
it
and
there's
a
port
in
progress.
I
believe
he's
here,
but
I
don't
know
how
far
that's
come
along
and
also
Gen
2
I
submitted
an
arch
named
for
Gen
2,
but
we
don't
have
any
packages
so
well.
Technically,
we
have
a
port,
it
doesn't
work,
that's
how
it
always
goes.
B
Okay,
so
the
real
key
here
is
that
if
you
are
interested
in
any
of
these
projects
or
really
any
other
project,
now
is
the
time
to
get
started.
Porting
your
favorite
projects
to
risk
five,
because
it's
a
free
and
open
ISA
and
the
only
way
we
can
make
this
work
is,
if
we
have
support
from
the
whole
community
in
soft
reporting
is
a
huge
effort.
As
I'm
sure
everybody
else
now,
in
addition
to
new
software
reports
coming
out,
the
risk
5
foundation
is
also
working
on
new
specifications.
B
Now
one
of
these
interests,
one
particular
interesting
one-
is
the
V
extension
which
is
for
it
was
an
advanced
vector
extensions.
So
it's
based
on
a
Cray
style
vector,
but
it's
kind
of
been
updated
for
the
modern
world.
It's
targeted
for
both
spatial
and
temporal
vector
machines,
which
is
interesting
because,
usually
you
have
per
say,
you
know,
different
spatial
Simbi
machines.
You
have
very
different
vector
ISAs
as
you
move
to
longer
widths,
but
the
goal
here
is
to
have
a
single
is
a
they
can
execute
across
all
all
classes
of
machines.
B
Much
like
how
the
risk
drive
user
is
a
can
execute
from
small
embedded
microcontrollers
to
large
super
computers.
The
same
thing,
if
you
are
a
say,
LOV,
M,
vectorizing,
compiler
expert
or
a
GCC
vectorizing,
a
filer
expert.
This
is
a
great
time
to
start
working
on
a
real,
cutting-edge
vector
is
a
without
all
the
headaches
of
the
existing
one.
B
There's
was
a
presentation
about
this
at
the
risk
5
workshop
in
last
December,
December
of
2017
and
there's
a
draft
expected
by
the
end
of
you
now,
additionally,
we're
working
on
something
called
the
J
extension,
which
is
for
advanced
jets,
and
this
really
means
JVM
is
like
open
JDK.
So
there's
also
a
standards
process
going
through
with
this,
and
if
you're
interested
in
working
on,
say
a
JDK
for
risk.
B
5
now
would
be
a
great
time
to
start,
because
the
standards
body,
the
the
working
group
which
which
writes
the
I/o
say
extension,
is
just
me
informed
now,
so
you
can
hop
on
the
mailing
list,
be
part
of
the
J
extensions
from
the
start
and
help
port
help
help
port
a
job
implantation
to
respond.
So
in
addition
to
that,
we're
working
on
something
called
the
UNIX
platform
specification.
B
B
B
B
So
it's
running
the
full
risk:
5
Linux
software
stack,
so
it's
running
in
Ex,
hardware,
accelerated,
graphics
and
PCI,
Express
and
whatnot,
and
this
is
so
cutting
edge
that
Young's
up
in
order
to
get
the
board
here
on
time
had
to
fly
to
FOSDEM
the
day
after
me,
because
we
couldn't
get
the
chip
stuck
on
the
board
in
time
for
my
flight
and
he's
very
excited
to
come
and
give
you
a
few
words
and
after
that,
we'll
give
you
a
demo.
So
I
can
actually
prove
to
you
that
this
is
running
a
real
risk.
C
As
a
matter
of
fact,
you
know
it
came
out
of
the
fab
2
days
ago,
so
you
know
you
guys
are
the
first
audience
to
actually
see
it.
You
know
so
this
is
really
cutting
edge.
So
what's
on
the
board,
so
in
the
middle
you
can
see
the
sci-fi
freedom
unleashed
540
chip,
it's
the
it's
a
first
stepping
of
the
chip
it's
built
in
28
nanometers.
It
has
for
64-bit
application
cores
which
implements
the
RV
64.
C
So,
for
example,
today
we
have
mounted
this
board
on
a
VGA
which
supports
PCIe
and
that
is
supporting
all
the
graphics,
the
SSD,
as
well
as
the
clicker.
As
a
matter
of
fact,
so
at
the
end
of
the
talk
you
will
see
a
demo
with
accelerated
graphics
and
obviously
you
know.
The
first
thing
that
we
have
to
show
is
quake
ready
on
the
actual
chip.
C
C
Chip
there,
so
this
is
a
block
diagram,
as
I
told
you
there's
one
Ecore
and
for
you
course,
and
in
the
middle
there's
the
coherent,
l2
cache
and
a
bunch
of
low-speed
peripherals
on
on
the
right,
as
well
as
the
pob
Ethernet,
there's
OTP.
There's
there's
mask
ROM
and
notice
that
all
the
components
on
the
SOC
are
connected
with
tiling,
so
tile
ink
is
a
free
and
open
SOC
interconnect
standard
that
we
started
building
from
Berkeley
days.
So
all
the
specs
are
online.
C
C
C
So
the
fu
540
chip
is
an
instantiation
of
the
freedom
platform,
which
is
a
open-source
wrist
5
base,
as
the
C
platform
maintained
by
Sai
5.
So
in
the
freedom
platform,
what's
inside
it,
so
we
have
open
source
to
risk
by
rocket
CPU
and
the
tile
link
the
free
and
open
Internet
that
I've
told
you
and
a
bunch
of
low
speed
peripherals
like
spy.
C
So,
as
I
told
you,
the
freedom,
Unleashed
540
chip
is
based
on
the
freedom
platform,
but
unfortunately
there
are
things
that
we
have.
We
can't
open
source,
for
example,
the
things
that
we
got,
the
IPS
that
we
got
from
the
third
parties,
such
as
a
standard
cells,
the
pads
the
PLL's
otps
damask
rounds,
the
DVR
controller
5
that
gigabit
mac.
So
I
have
you
know.
Sadly,
I
have
to
point
out
that
the
chip,
the
efi
540,
is
not
a
direct
instantiation
of
the
freedom
platform.
C
So
what
can
you
do
with
this?
Well,
you
can
map
the
freedom
platforms
onto
FPGAs.
So,
for
example,
we
can
map
the
freedom
everywhere
platform
on
an
$99
rd
board
and
you
can
its
Arduino
shield
compatible.
So
you
can,
you
know
plug
in
a
lot
of
things
and
also
for
the
Freedom
Unleashed
platform.
You
can
map
the
platform
onto
the
vc
707,
which
has
DRAM
and
PCIe,
and
things
like
that,
so
you
can
run
doom
on
it
and
so
what
you
can
do
is
you
can
customize
your
freedom
platform
for
your
needs
and
sy5.
C
C
C
C
Ok,
now
we're
gonna
go
see
the
exciting
demo
and
after
the
demo,
we're
gonna
have
a
quick
Q&A
session,
and
if
it
you
know,
if
you
have,
if
you
have
a
lot
of
questions
and
want
to
talk
to
us,
there's
actually
a
Boff
session
after
this
from
6:00
to
7:00
at
this
room
location,
so
I'll
see
you,
there
I
believe
the
wrist
Fire
readers
are
gonna,
be
given
to
the
winners
there
so
well
we'll
go
check
it
out
there.
So
thank
you
very
much.
C
C
B
B
B
We're
finding
some
issues,
but
nothing
super
major,
so
hopefully
it'll
be
in
soon
there's
something
called
freedom,
you
SDK,
which
is
the
SDK
that
goes
along
with
the
board,
and
that
has
a
Linux
version,
that's
known
to
work
in
a
tool
chain,
that's
known
to
work
and
some
bootloader
stuff.
And
if
you
go
in
there
and
you
type
make
QAM
you
it
will
boot
and
qmu
with
a
disk,
and
you
can
do
whatever
you
want.
It's
a
build
root
base.
G
Question
and
you
proxy
P
you
info
I,
saw,
for
course
you
also
have
a
management
core.
What
does
the
management
core
do
and
have
you
heard
of
the
concept
of
a
donkey
engine
which
is
a
small
engine?
You
used
to
start
a
very
big
marine
diesel
engine?
Yes,
so
I
walk
in
high
performance
computing
and
have
always
said
that
we
need.
We
need
chips
where
you
have
a
cause
that
working
flat
out
doing
computations,
but
you
need
a
smaller
core,
actually
running
the
operating
system
and
doing
the
housekeeping.
B
So
the
question
is:
what
what
does
the
fifth
chord?
Do?
You
only
see
five
cores
and
proxy
PU
info
so
right
now
it's
asleep
it's
supposed
to
be
a
power
management
unit,
but
we
don't
have
that
implemented
right
now,
but
the
idea
is
that,
yes,
if
you
wanted
to
build
for
HPC
systems
with
you
know
additional
cores
to
run
the
operating
system,
that'd
be
a
great
opportunity
for
customizing
a
risk,
five
chip
and
that's
something
we
we
do
and
that's
a
lot
of
people
aren't
just
in
that
sort
of
thing.
H
Obama,
thank
you
for
a
talk
great
to
hear
the
progress.
I'm,
glad
that
we're
part
of
the
work
on
that
tool
chain
can
I
just
pick
you
up
on
one
thing
and
you
do
you
describe
risk
five
as
the
first
free
and
open
icer.
How
do
you
see
risk
five
compared
to
open
risk
because
I'm
sure
the
open
risk
guys
would
feel
that
much
as
most
of
them
are
working
on
risk?
Five?
Now
they
possibly
were
there
before
you
so.
B
C
I
C
B
J
So
so
you
sat
at
suitable
housing
risk,
five
from
the
smallest
to
the
biggest
machines
now
I've
seen
a
lot
of
8-bit
was
replaced
by
I'm,
sorry
bit
stuff,
but
the
8-bit
us
are
still.
They
are
I.
Believe
you
with
your
coats,
I
stuff.
You
can
easily
replace
the
arms
on
the
my
small
microcontrollers,
but
how
about
the
8-bit?
Does
we
list
five
replace
him
or
do
we
need
another
initiative
like
this
five,
this
time
aimed
at
8-bit
microcontrollers?
J
C
Risk
5
will
be
bigger
than
they
fit.
Microcontroller
slightly
I.
Think
I,
think
one
perspective,
I
want
to
say
is
I,
think
a
lot
of
the
microcontrollers
doing
more
computation
and
things
like
that.
Obviously
there
are
applications
where
API
controllers
do
just
fine
and
I
think
you
know.
Ris
five
will
do
okay
on
those
things,
but
it
would
be
hard
to
beat
the
8-bit
microcontrollers,
but
if
you're
needing
more
compute
power
and
things
like
that,
I
think
the
this
32-bit
risc
5
is
a
fine
target
for
those
type
of
applications.
K
8-Bit
us,
if
you
think
about
the
pet
size
you
need
for
for
connecting
to
the
chip,
it
really
doesn't
make
sense
with
the
current
process
to
use
8-bit
us,
because
the
pet
sizes
are
so
much
so
large
compared
to
the
core
that
the
price
for
32-bit
doesn't
matter
anymore.
But
I
have
another
question:
what's
the
power
point
I've
seen
of
the
chip
I've
seen
heat
mount.
K
C
You're
very
sharp
and
was
paying
attention
to
the
talk.
Yes,
so
the
the
board
is
the
first
revision,
so
we
I
developed
the
board
to
put
a
socket
in
so
that
we
can.
You
know,
test
multiple
chips,
but
yeah
great
catch.
It's
now
for
the
heatsink.
We,
you
know
we
we're
not
burning
hundred
thirty-five
watts.
B
B
Yeah
but
yeah
that
that's
why
we
have
the
little
cart
because
there's
a
lot
of
stuff
yeah,
so
there's
there's
a
there's,
an
AMD
graphics
card.
In
there
it's
a
Caicos
pace
car,
it's
a
few
years
old,
it's
one
of
the
ones
we
could
find
a
boot
with
very
minimal
firmware
and
that
sort
of
stuff,
so
right
yeah
it
kind
of
kind
of
even
works
yeah,
so
so
so
so
yeah.
So
that's
doing
the
vast
majority
of
the
rendering.
G
B
So
it's
just
using
the
you
know:
regular
kernel
drivers
at
the
kms
in
DRM
and
then
meza
in
user
space
and
that
kind
of
all
just
compiles
and
more
or
less
works
out
of
the
box.
We
don't
we've
been
a
lot
of
pushing
on
our
kernel
port
over
the
last
say
year
to
get
kind
of
devices
up
and
running,
and
it's
at
the
point
where,
like
when
I
first
started
working
on
this
stuff.
B
If
you
ran
something
you
hadn't
run
before
like
there's
no
way
it
would
work
now,
when
you
run
something
you
haven't
run
before
it
might
work
like
quake
kind
of
just
worked
the
hardest
part
to
getting
it
to
work
was
figuring
out
how
to
get
it
to
go.
Fullscreen
because
I
know
that
command-line
options.
C
L
B
So
the
question
was:
how
do
we
make
sure
the
ABI
won't
change
again
and
how
to
make
sure
the
platform
specs
are
set,
so
they
won't
change
again,
so
I
mean
the
ABI
won't
change
again
because
we're
just
saying
it
won't
change
again.
It's
done
it's.
Never
it's
not
changing.
That's
it!
That's
kind
of
how
you
make
it
not
changes.
You
just
say
it
doesn't
change
for
the
platform
specification
right
so
before
when
we
were
not
upstream,
we
hadn't
put
a
stake
in
the
ground
saying
the
ABI
is
not
changing.
B
Now
there
we
are
upstream,
it's
like
every
other
port
remaining
containing
api
compatibility
kind
of
forever,
as
far
as
I
know
as
long
as
I'm
around
at
least
so,
and
then
for
the
platform
classifications,
because
there
is
no
platform
spec,
there's
kind
of
there's
nothing
there,
but
we're
producing
one.
The
risk
by
platforms
that
exists
are
simple
enough,
that
the
hope
is
that
we
can
ensure
that
they
will.
You
know,
match
up
with
a
platform
spec
well
enough,
that
they
can
boot
things
and
you
can
discover
what's
there
and
whatnot,
but
that's
kind
of
it.
B
That
would
be
a
great
way
to
get
involved
if
you're
interested
in
so
the
platform
specifications.
That's
something!
That's
gonna,
be
a
lot
of
work
over
the
next
say
a
few
months
to
year,
and
it's
really
important
stuff,
because
we
don't
want
it
to
go
the
wrong
way,
because
I
can
have
a
lot
of
headaches.
I
First
I
wanted
to
say
thank
you
for
making
it
a
free
and
open
design.
That's
fantastic!
It's
great
that
that
sort
of
thing
exists.
Now
and
recently
you
know
there
were
processors
that
had
issues
due
to
the
specter
in
meltdown
bugs
and
I'm
curious
to
know
when
people,
when
people
wanted
to
mitigate
that.
I
One
of
the
things
that
you
have
to
do
on
some
systems
is
install
firmware
enough
firmware,
but
a
micro
code
update
and
that
micro
code
is
usually
non
free
and
I'm
curious
to
know
if
the
issue
of
free
versus
non
free
micro
code
is
orthogonal
to
having
a
designer.
If
you
feel
that
having
a
free
and
open
design
facilitates
the
creation
of
you
know:
free
micro
code
updates,
that's.
C
C
That's
that's
a
great
question,
so
the
u54
is
a
single
issue
in
order
pipeline.
So
but
it's
a
64-bit
pipeline,
so
it's
somewhere
between
you
know,
arm
I,
think
a
35
and
a
53
somewhere
in
between
that
and
the
processors
can
run
up
to
1.5
gigahertz
in
terms
of
frequency,
so
the
e3
51,
the
bookkeeping
core
that
was
on
the
side,
doesn't
have
an
MMU
and
that
resembles
more
of
a
court
I'm
series
and
that
is
similar
to
M,
2020,
23
and
m33
s.